Unified Coverage Report :: Module :: uart_reg_top

Module : uart_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.52	100.00	98.06			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.52	100.00	98.06			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.52	100.00	98.06			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.40	99.52	98.71	93.78		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
33.14	0.00	0.00	99.43				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_ctrl_llpbk	100.00	100.00	100.00			100.00
u_ctrl_nco	100.00	100.00	100.00			100.00
u_ctrl_nf	100.00	100.00	100.00			100.00
u_ctrl_parity_en	100.00	100.00	100.00			100.00
u_ctrl_parity_odd	100.00	100.00	100.00			100.00
u_ctrl_rx	100.00	100.00	100.00			100.00
u_ctrl_rxblvl	100.00	100.00	100.00			100.00
u_ctrl_slpbk	100.00	100.00	100.00			100.00
u_ctrl_tx	100.00	100.00	100.00			100.00
u_fifo_ctrl0_qe	100.00	100.00				100.00
u_fifo_ctrl_rxilvl	96.30	100.00	88.89			100.00
u_fifo_ctrl_rxrst	100.00	100.00	100.00			100.00
u_fifo_ctrl_txilvl	96.30	100.00	88.89			100.00
u_fifo_ctrl_txrst	100.00	100.00	100.00			100.00
u_fifo_status_rxlvl	100.00	100.00
u_fifo_status_txlvl	100.00	100.00
u_intr_enable_rx_break_err	100.00	100.00	100.00			100.00
u_intr_enable_rx_frame_err	100.00	100.00	100.00			100.00
u_intr_enable_rx_overflow	100.00	100.00	100.00			100.00
u_intr_enable_rx_parity_err	100.00	100.00	100.00			100.00
u_intr_enable_rx_timeout	100.00	100.00	100.00			100.00
u_intr_enable_rx_watermark	100.00	100.00	100.00			100.00
u_intr_enable_tx_empty	100.00	100.00	100.00			100.00
u_intr_enable_tx_watermark	100.00	100.00	100.00			100.00
u_intr_state_rx_break_err	100.00	100.00	100.00			100.00
u_intr_state_rx_frame_err	100.00	100.00	100.00			100.00
u_intr_state_rx_overflow	100.00	100.00	100.00			100.00
u_intr_state_rx_parity_err	100.00	100.00	100.00			100.00
u_intr_state_rx_timeout	100.00	100.00	100.00			100.00
u_intr_state_rx_watermark	100.00	100.00	100.00			100.00
u_intr_state_tx_empty	100.00	100.00	100.00			100.00
u_intr_state_tx_watermark	100.00	100.00	100.00			100.00
u_intr_test_rx_break_err	100.00	100.00
u_intr_test_rx_frame_err	100.00	100.00
u_intr_test_rx_overflow	100.00	100.00
u_intr_test_rx_parity_err	100.00	100.00
u_intr_test_rx_timeout	100.00	100.00
u_intr_test_rx_watermark	100.00	100.00
u_intr_test_tx_empty	100.00	100.00
u_intr_test_tx_watermark	100.00	100.00
u_ovrd_txen	100.00	100.00	100.00			100.00
u_ovrd_txval	100.00	100.00	100.00			100.00
u_prim_reg_we_check	50.00	100.00		0.00
u_rdata	66.67	66.67
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_status_rxempty	100.00	100.00
u_status_rxfull	100.00	100.00
u_status_rxidle	100.00	100.00
u_status_txempty	100.00	100.00
u_status_txfull	100.00	100.00
u_status_txidle	100.00	100.00
u_timeout_ctrl_en	100.00	100.00	100.00			100.00
u_timeout_ctrl_val	100.00	100.00	100.00			100.00
u_val	100.00	100.00
u_wdata	100.00	100.00	100.00			100.00
u_wdata0_qe	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : uart_reg_top

	Line No.	Total	Covered	Percent
TOTAL		168	168	100.00
ALWAYS	71	4	4	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	665	1	1	100.00
CONT_ASSIGN	680	1	1	100.00
CONT_ASSIGN	696	1	1	100.00
CONT_ASSIGN	712	1	1	100.00
CONT_ASSIGN	728	1	1	100.00
CONT_ASSIGN	744	1	1	100.00
CONT_ASSIGN	760	1	1	100.00
CONT_ASSIGN	776	1	1	100.00
CONT_ASSIGN	792	1	1	100.00
CONT_ASSIGN	798	1	1	100.00
CONT_ASSIGN	812	1	1	100.00
CONT_ASSIGN	1205	1	1	100.00
CONT_ASSIGN	1246	1	1	100.00
CONT_ASSIGN	1274	1	1	100.00
CONT_ASSIGN	1302	1	1	100.00
CONT_ASSIGN	1330	1	1	100.00
ALWAYS	1496	14	14	100.00
CONT_ASSIGN	1512	1	1	100.00
ALWAYS	1516	1	1	100.00
CONT_ASSIGN	1533	1	1	100.00
CONT_ASSIGN	1535	1	1	100.00
CONT_ASSIGN	1537	1	1	100.00
CONT_ASSIGN	1539	1	1	100.00
CONT_ASSIGN	1541	1	1	100.00
CONT_ASSIGN	1543	1	1	100.00
CONT_ASSIGN	1545	1	1	100.00
CONT_ASSIGN	1547	1	1	100.00
CONT_ASSIGN	1549	1	1	100.00
CONT_ASSIGN	1550	1	1	100.00
CONT_ASSIGN	1552	1	1	100.00
CONT_ASSIGN	1554	1	1	100.00
CONT_ASSIGN	1556	1	1	100.00
CONT_ASSIGN	1558	1	1	100.00
CONT_ASSIGN	1560	1	1	100.00
CONT_ASSIGN	1562	1	1	100.00
CONT_ASSIGN	1564	1	1	100.00
CONT_ASSIGN	1566	1	1	100.00
CONT_ASSIGN	1567	1	1	100.00
CONT_ASSIGN	1569	1	1	100.00
CONT_ASSIGN	1571	1	1	100.00
CONT_ASSIGN	1573	1	1	100.00
CONT_ASSIGN	1575	1	1	100.00
CONT_ASSIGN	1577	1	1	100.00
CONT_ASSIGN	1579	1	1	100.00
CONT_ASSIGN	1581	1	1	100.00
CONT_ASSIGN	1583	1	1	100.00
CONT_ASSIGN	1584	1	1	100.00
CONT_ASSIGN	1586	1	1	100.00
CONT_ASSIGN	1587	1	1	100.00
CONT_ASSIGN	1589	1	1	100.00
CONT_ASSIGN	1591	1	1	100.00
CONT_ASSIGN	1593	1	1	100.00
CONT_ASSIGN	1595	1	1	100.00
CONT_ASSIGN	1597	1	1	100.00
CONT_ASSIGN	1599	1	1	100.00
CONT_ASSIGN	1601	1	1	100.00
CONT_ASSIGN	1603	1	1	100.00
CONT_ASSIGN	1605	1	1	100.00
CONT_ASSIGN	1606	1	1	100.00
CONT_ASSIGN	1607	1	1	100.00
CONT_ASSIGN	1608	1	1	100.00
CONT_ASSIGN	1610	1	1	100.00
CONT_ASSIGN	1611	1	1	100.00
CONT_ASSIGN	1613	1	1	100.00
CONT_ASSIGN	1615	1	1	100.00
CONT_ASSIGN	1617	1	1	100.00
CONT_ASSIGN	1619	1	1	100.00
CONT_ASSIGN	1620	1	1	100.00
CONT_ASSIGN	1621	1	1	100.00
CONT_ASSIGN	1623	1	1	100.00
CONT_ASSIGN	1625	1	1	100.00
CONT_ASSIGN	1626	1	1	100.00
CONT_ASSIGN	1627	1	1	100.00
CONT_ASSIGN	1629	1	1	100.00
CONT_ASSIGN	1631	1	1	100.00
ALWAYS	1635	14	14	100.00
ALWAYS	1653	55	55	100.00
CONT_ASSIGN	1758	0	0
CONT_ASSIGN	1766	1	1	100.00
CONT_ASSIGN	1767	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_reg_top.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
80	1	1
92	1	1
93	1	1
121	1	1
122	1	1
665	1	1
680	1	1
696	1	1
712	1	1
728	1	1
744	1	1
760	1	1
776	1	1
792	1	1
798	1	1
812	1	1
1205	1	1
1246	1	1
1274	1	1
1302	1	1
1330	1	1
1496	1	1
1497	1	1
1498	1	1
1499	1	1
1500	1	1
1501	1	1
1502	1	1
1503	1	1
1504	1	1
1505	1	1
1506	1	1
1507	1	1
1508	1	1
1509	1	1
1512	1	1
1516	1	1
1533	1	1
1535	1	1
1537	1	1
1539	1	1
1541	1	1
1543	1	1
1545	1	1
1547	1	1
1549	1	1
1550	1	1
1552	1	1
1554	1	1
1556	1	1
1558	1	1
1560	1	1
1562	1	1
1564	1	1
1566	1	1
1567	1	1
1569	1	1
1571	1	1
1573	1	1
1575	1	1
1577	1	1
1579	1	1
1581	1	1
1583	1	1
1584	1	1
1586	1	1
1587	1	1
1589	1	1
1591	1	1
1593	1	1
1595	1	1
1597	1	1
1599	1	1
1601	1	1
1603	1	1
1605	1	1
1606	1	1
1607	1	1
1608	1	1
1610	1	1
1611	1	1
1613	1	1
1615	1	1
1617	1	1
1619	1	1
1620	1	1
1621	1	1
1623	1	1
1625	1	1
1626	1	1
1627	1	1
1629	1	1
1631	1	1
1635	1	1
1636	1	1
1637	1	1
1638	1	1
1639	1	1
1640	1	1
1641	1	1
1642	1	1
1643	1	1
1644	1	1
1645	1	1
1646	1	1
1647	1	1
1648	1	1
1653	1	1
1654	1	1
1656	1	1
1657	1	1
1658	1	1
1659	1	1
1660	1	1
1661	1	1
1662	1	1
1663	1	1
1667	1	1
1668	1	1
1669	1	1
1670	1	1
1671	1	1
1672	1	1
1673	1	1
1674	1	1
1678	1	1
1679	1	1
1680	1	1
1681	1	1
1682	1	1
1683	1	1
1684	1	1
1685	1	1
1689	1	1
1693	1	1
1694	1	1
1695	1	1
1696	1	1
1697	1	1
1698	1	1
1699	1	1
1700	1	1
1701	1	1
1705	1	1
1706	1	1
1707	1	1
1708	1	1
1709	1	1
1710	1	1
1714	1	1
1718	1	1
1722	1	1
1723	1	1
1724	1	1
1725	1	1
1729	1	1
1730	1	1
1734	1	1
1735	1	1
1739	1	1
1743	1	1
1744	1	1
1758		unreachable
1766	1	1
1767	1	1

---

Cond Coverage for Module : uart_reg_top

	Total	Covered	Percent
Conditions	155	152	98.06
Logical	155	152	98.06
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T13,T5
1	1	Covered	T1,T2,T3

 LINE       73
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T4,T24

 LINE       80
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T1,T4,T24
1	0	0	Covered	T1,T4,T24

 LINE       122
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T4,T24
0	1	0	Covered	T13,T5,T14
1	0	0	Covered	T13,T5,T14

 LINE       122
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T13

 LINE       1497
 EXPRESSION (reg_addr == uart_reg_pkg::UART_INTR_STATE_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1498
 EXPRESSION (reg_addr == uart_reg_pkg::UART_INTR_ENABLE_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1499
 EXPRESSION (reg_addr == uart_reg_pkg::UART_INTR_TEST_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1500
 EXPRESSION (reg_addr == uart_reg_pkg::UART_ALERT_TEST_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1501
 EXPRESSION (reg_addr == uart_reg_pkg::UART_CTRL_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1502
 EXPRESSION (reg_addr == uart_reg_pkg::UART_STATUS_OFFSET)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1503
 EXPRESSION (reg_addr == uart_reg_pkg::UART_RDATA_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1504
 EXPRESSION (reg_addr == uart_reg_pkg::UART_WDATA_OFFSET)
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1505
 EXPRESSION (reg_addr == uart_reg_pkg::UART_FIFO_CTRL_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1506
 EXPRESSION (reg_addr == uart_reg_pkg::UART_FIFO_STATUS_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1507
 EXPRESSION (reg_addr == uart_reg_pkg::UART_OVRD_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1508
 EXPRESSION (reg_addr == uart_reg_pkg::UART_VAL_OFFSET)
            ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1509
 EXPRESSION (reg_addr == uart_reg_pkg::UART_TIMEOUT_CTRL_OFFSET)
            --------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1512
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1512
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       1516
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T13

 LINE       1516
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b0111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	0	0	0	0	0	0	0	1	Covered	T1,T3,T4
0	0	0	0	0	0	0	0	0	0	0	1	0	Covered	T1,T3,T4
0	0	0	0	0	0	0	0	0	0	1	0	0	Covered	T1,T3,T4
0	0	0	0	0	0	0	0	0	1	0	0	0	Covered	T1,T3,T4
0	0	0	0	0	0	0	0	1	0	0	0	0	Covered	T1,T3,T13
0	0	0	0	0	0	0	1	0	0	0	0	0	Covered	T1,T3,T13
0	0	0	0	0	0	1	0	0	0	0	0	0	Covered	T1,T13,T5
0	0	0	0	0	1	0	0	0	0	0	0	0	Covered	T1,T3,T4
0	0	0	0	1	0	0	0	0	0	0	0	0	Covered	T1,T3,T4
0	0	0	1	0	0	0	0	0	0	0	0	0	Covered	T1,T3,T4
0	0	1	0	0	0	0	0	0	0	0	0	0	Covered	T1,T13,T5
0	1	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T3,T4
1	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T3

 LINE       1516
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       1516
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       1516
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T13,T5

 LINE       1516
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       1516
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       1516
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       1516
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T13,T5

 LINE       1516
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T13

 LINE       1516
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T13

 LINE       1516
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       1516
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       1516
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       1516
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       1533
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T5,T16
1	1	1	Covered	T12,T7,T8

 LINE       1550
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T14,T16
1	1	1	Covered	T1,T2,T3

 LINE       1567
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T13,T5,T16
1	1	1	Covered	T7,T8,T9

 LINE       1584
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T13,T16
1	1	1	Covered	T1,T2,T3

 LINE       1587
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T24,T16
1	1	1	Covered	T1,T2,T3

 LINE       1606
 EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T24,T58
1	1	1	Covered	T1,T2,T3

 LINE       1607
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T20,T59,T53
1	1	1	Not Covered

 LINE       1608
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T13,T5,T16
1	1	1	Covered	T10,T6,T36

 LINE       1611
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T13,T24,T16
1	1	1	Covered	T1,T2,T3

 LINE       1620
 EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T4,T59,T60
1	1	1	Covered	T1,T2,T3

 LINE       1621
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T5,T16,T17
1	1	1	Covered	T1,T2,T3

 LINE       1626
 EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T20,T59
1	1	1	Covered	T1,T2,T3

 LINE       1627
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T13,T16,T17
1	1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : uart_reg_top

	Line No.	Total	Covered	Percent
Branches		19	19	100.00
TERNARY	1512	2	2	100.00
IF	71	3	3	100.00
CASE	1654	14	14	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_reg_top.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1512	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	71	if ((!rst_ni))
-2-:	73	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T4,T24
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1654	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : uart_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	550411	28679	0	0
reAfterRv	550411	28677	0	0
rePulse	550411	17183	0	0
wePulse	550411	11494	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	550411	28679	0	0
T1	11039	338	0	0
T2	1716	113	0	0
T3	2644	88	0	0
T4	4667	334	0	0
T5	9217	18	0	0
T7	1554	40	0	0
T12	16584	2291	0	0
T13	4646	19	0	0
T14	2108	77	0	0
T15	1171	73	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	550411	28677	0	0
T1	11039	338	0	0
T2	1716	113	0	0
T3	2644	88	0	0
T4	4667	334	0	0
T5	9217	18	0	0
T7	1554	40	0	0
T12	16584	2291	0	0
T13	4646	19	0	0
T14	2108	76	0	0
T15	1171	73	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	550411	17183	0	0
T1	11039	237	0	0
T2	1716	52	0	0
T3	2644	69	0	0
T4	4667	234	0	0
T5	9217	2	0	0
T7	1554	20	0	0
T12	16584	1146	0	0
T13	4646	10	0	0
T14	2108	55	0	0
T15	1171	38	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	550411	11494	0	0
T1	11039	101	0	0
T2	1716	61	0	0
T3	2644	19	0	0
T4	4667	100	0	0
T5	9217	16	0	0
T7	1554	20	0	0
T12	16584	1145	0	0
T13	4646	9	0	0
T14	2108	21	0	0
T15	1171	35	0	0