Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
33.14	0.00	0.00	99.43				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	550411	13268	0	0
ctrl_rd_A	550411	2245	0	0
intr_enable_rd_A	550411	2390	0	0
ovrd_rd_A	550411	1354	0	0
timeout_ctrl_rd_A	550411	1311	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550411	13268	0	0
T1	11039	2	0	0
T2	1716	0	0	0
T3	2644	34	0	0
T4	4667	1	0	0
T5	9217	492	0	0
T7	1554	0	0	0
T12	16584	0	0	0
T13	4646	393	0	0
T14	2108	159	0	0
T15	1171	0	0	0
T16	0	459	0	0
T24	0	2	0	0
T27	0	26	0	0
T32	0	6	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550411	2245	0	0
T7	1554	0	0	0
T8	994	0	0	0
T9	1492	0	0	0
T15	1171	2	0	0
T16	3923	0	0	0
T22	1381	0	0	0
T23	652	0	0	0
T24	3783	0	0	0
T27	0	5	0	0
T33	0	80	0	0
T36	0	5	0	0
T37	0	11	0	0
T40	0	18	0	0
T50	0	9	0	0
T56	1016	0	0	0
T57	1911	0	0	0
T61	0	10	0	0
T62	0	47	0	0
T63	0	16	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550411	2390	0	0
T7	1554	0	0	0
T8	994	0	0	0
T9	1492	23	0	0
T11	0	12	0	0
T15	1171	9	0	0
T16	3923	0	0	0
T22	1381	0	0	0
T23	652	0	0	0
T24	3783	0	0	0
T27	0	12	0	0
T33	0	30	0	0
T40	0	44	0	0
T56	1016	0	0	0
T57	1911	0	0	0
T61	0	31	0	0
T64	0	3	0	0
T65	0	9	0	0
T66	0	30	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550411	1354	0	0
T7	1554	0	0	0
T8	994	0	0	0
T9	1492	0	0	0
T15	1171	17	0	0
T16	3923	0	0	0
T22	1381	0	0	0
T23	652	0	0	0
T24	3783	0	0	0
T27	0	15	0	0
T33	0	12	0	0
T36	0	7	0	0
T37	0	14	0	0
T40	0	14	0	0
T50	0	8	0	0
T56	1016	0	0	0
T57	1911	0	0	0
T61	0	22	0	0
T62	0	21	0	0
T63	0	21	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550411	1311	0	0
T7	1554	0	0	0
T8	994	0	0	0
T9	1492	0	0	0
T15	1171	6	0	0
T16	3923	0	0	0
T22	1381	0	0	0
T23	652	0	0	0
T24	3783	0	0	0
T27	0	9	0	0
T33	0	9	0	0
T36	0	3	0	0
T37	0	7	0	0
T40	0	80	0	0
T50	0	13	0	0
T56	1016	0	0	0
T57	1911	0	0	0
T61	0	25	0	0
T62	0	3	0	0
T63	0	8	0	0