Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.45	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	2	30	93.75

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	2	30	93.75	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	344	1			T2	8		T6	5		T12	1
all_values[1]	344	1			T2	8		T6	5		T12	1
all_values[2]	344	1			T2	8		T6	5		T12	1
all_values[3]	344	1			T2	8		T6	5		T12	1
all_values[4]	344	1			T2	8		T6	5		T12	1
all_values[5]	344	1			T2	8		T6	5		T12	1
all_values[6]	344	1			T2	8		T6	5		T12	1
all_values[7]	344	1			T2	8		T6	5		T12	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1544

1

T2

34

T6

20

T12

8

auto[1]

1208

1

T2

30

T6

20

T8

26

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1557

1

T2

29

T6

18

T12

7

auto[1]

1195

1

T2

35

T6

22

T12

1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	2	30	93.75	2

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	191	1			T2	4		T6	5		T12	1
all_values[0]	auto[1]	auto[1]	153	1			T2	4		T8	4		T29	4
all_values[1]	auto[0]	auto[0]	124	1			T2	2		T12	1		T13	1
all_values[1]	auto[0]	auto[1]	54	1			T2	3		T10	2		T9	1
all_values[1]	auto[1]	auto[0]	108	1			T2	1		T6	4		T8	3
all_values[1]	auto[1]	auto[1]	58	1			T2	2		T6	1		T8	2
all_values[2]	auto[0]	auto[0]	121	1			T6	1		T12	1		T8	5
all_values[2]	auto[0]	auto[1]	76	1			T6	3		T29	1		T10	3
all_values[2]	auto[1]	auto[0]	96	1			T2	5		T29	1		T10	2
all_values[2]	auto[1]	auto[1]	51	1			T2	3		T6	1		T9	2
all_values[3]	auto[0]	auto[0]	141	1			T2	2		T6	3		T12	1
all_values[3]	auto[0]	auto[1]	55	1			T2	1		T10	3		T9	4
all_values[3]	auto[1]	auto[0]	89	1			T2	1		T6	1		T8	4
all_values[3]	auto[1]	auto[1]	59	1			T2	4		T6	1		T29	2
all_values[4]	auto[0]	auto[0]	125	1			T2	5		T6	1		T12	1
all_values[4]	auto[0]	auto[1]	75	1			T2	1		T8	1		T29	1
all_values[4]	auto[1]	auto[0]	89	1			T2	1		T6	1		T8	1
all_values[4]	auto[1]	auto[1]	55	1			T2	1		T6	3		T8	3
all_values[5]	auto[0]	auto[0]	134	1			T2	1		T12	1		T8	1
all_values[5]	auto[0]	auto[1]	69	1			T2	5		T8	1		T29	1
all_values[5]	auto[1]	auto[0]	85	1			T6	2		T8	1		T10	1
all_values[5]	auto[1]	auto[1]	56	1			T2	2		T6	3		T8	2
all_values[6]	auto[0]	auto[0]	130	1			T2	4		T6	2		T12	1
all_values[6]	auto[0]	auto[1]	60	1			T2	1		T6	3		T8	2
all_values[6]	auto[1]	auto[0]	95	1			T2	2		T8	1		T10	2
all_values[6]	auto[1]	auto[1]	59	1			T2	1		T10	3		T61	2
all_values[7]	auto[0]	auto[0]	120	1			T2	3		T6	2		T12	1
all_values[7]	auto[0]	auto[1]	69	1			T2	2		T10	2		T49	2
all_values[7]	auto[1]	auto[0]	100	1			T2	2		T6	1		T8	3
all_values[7]	auto[1]	auto[1]	55	1			T2	1		T6	2		T8	2