Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
65.74 64.27 63.16 96.20 63.37 100.00 7.41


Total tests in report: 165
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
61.79 61.79 61.56 61.56 54.88 54.88 97.12 97.12 59.52 59.52 96.37 96.37 1.28 1.28 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3314363626
64.46 2.67 63.96 2.40 60.32 5.44 98.95 1.83 62.41 2.89 96.70 0.33 4.41 3.13 /workspace/coverage/cover_reg_top/49.uart_intr_test.3185422127
65.39 0.93 64.17 0.21 62.05 1.73 99.48 0.52 62.65 0.24 97.03 0.33 6.97 2.56 /workspace/coverage/cover_reg_top/1.uart_tl_errors.39628069
65.96 0.57 64.27 0.10 62.67 0.62 99.48 0.00 63.37 0.72 99.01 1.98 6.97 0.00 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1691023752
66.08 0.12 64.27 0.00 62.67 0.00 99.48 0.00 63.37 0.00 99.67 0.66 7.02 0.04 /workspace/coverage/cover_reg_top/19.uart_csr_rw.381627502
66.13 0.06 64.27 0.00 62.67 0.00 99.48 0.00 63.37 0.00 100.00 0.33 7.02 0.00 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2242492548
66.18 0.05 64.27 0.00 62.67 0.00 99.48 0.00 63.37 0.00 100.00 0.00 7.30 0.28 /workspace/coverage/cover_reg_top/16.uart_intr_test.3152677276
66.23 0.04 64.27 0.00 62.92 0.25 99.48 0.00 63.37 0.00 100.00 0.00 7.32 0.02 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.4089707481
66.25 0.03 64.27 0.00 63.04 0.12 99.48 0.00 63.37 0.00 100.00 0.00 7.36 0.04 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.587492791
66.27 0.02 64.27 0.00 63.16 0.12 99.48 0.00 63.37 0.00 100.00 0.00 7.36 0.00 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1315331533
66.28 0.01 64.27 0.00 63.16 0.00 99.48 0.00 63.37 0.00 100.00 0.00 7.41 0.04 /workspace/coverage/cover_reg_top/12.uart_intr_test.3032860243

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.728562490
/workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1843969761
/workspace/coverage/cover_reg_top/0.uart_csr_rw.875125490
/workspace/coverage/cover_reg_top/0.uart_intr_test.1909214533
/workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1827427779
/workspace/coverage/cover_reg_top/0.uart_tl_errors.1381947347
/workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3179117802
/workspace/coverage/cover_reg_top/1.uart_csr_aliasing.541112352
/workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3682071287
/workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1617121748
/workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3960430747
/workspace/coverage/cover_reg_top/1.uart_csr_rw.2232036081
/workspace/coverage/cover_reg_top/1.uart_intr_test.2321315190
/workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2366137752
/workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2357129875
/workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1072459655
/workspace/coverage/cover_reg_top/10.uart_csr_rw.2574776281
/workspace/coverage/cover_reg_top/10.uart_intr_test.720116138
/workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.837978320
/workspace/coverage/cover_reg_top/10.uart_tl_errors.799417262
/workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.677520648
/workspace/coverage/cover_reg_top/11.uart_csr_rw.2537228290
/workspace/coverage/cover_reg_top/11.uart_intr_test.2163221471
/workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1377173604
/workspace/coverage/cover_reg_top/11.uart_tl_errors.2129561948
/workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1171831102
/workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.607074045
/workspace/coverage/cover_reg_top/12.uart_csr_rw.2308147172
/workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3382411560
/workspace/coverage/cover_reg_top/12.uart_tl_errors.483065321
/workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1814299948
/workspace/coverage/cover_reg_top/13.uart_csr_rw.2211324484
/workspace/coverage/cover_reg_top/13.uart_intr_test.780589201
/workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.662298781
/workspace/coverage/cover_reg_top/13.uart_tl_errors.2261684345
/workspace/coverage/cover_reg_top/13.uart_tl_intg_err.880107079
/workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2421035005
/workspace/coverage/cover_reg_top/14.uart_csr_rw.4006750713
/workspace/coverage/cover_reg_top/14.uart_intr_test.3858934866
/workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3662637858
/workspace/coverage/cover_reg_top/14.uart_tl_errors.1020425653
/workspace/coverage/cover_reg_top/14.uart_tl_intg_err.398847603
/workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2456006506
/workspace/coverage/cover_reg_top/15.uart_csr_rw.4001840582
/workspace/coverage/cover_reg_top/15.uart_intr_test.2658162695
/workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.4258888228
/workspace/coverage/cover_reg_top/15.uart_tl_errors.3470074301
/workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1761546948
/workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3056986023
/workspace/coverage/cover_reg_top/16.uart_csr_rw.2705591098
/workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2196166742
/workspace/coverage/cover_reg_top/16.uart_tl_errors.56295968
/workspace/coverage/cover_reg_top/16.uart_tl_intg_err.438356927
/workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2336824163
/workspace/coverage/cover_reg_top/17.uart_csr_rw.1673693742
/workspace/coverage/cover_reg_top/17.uart_intr_test.2227681596
/workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2243330089
/workspace/coverage/cover_reg_top/17.uart_tl_errors.2167701632
/workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3815723264
/workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1755106807
/workspace/coverage/cover_reg_top/18.uart_csr_rw.4005589873
/workspace/coverage/cover_reg_top/18.uart_intr_test.615998439
/workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.133940991
/workspace/coverage/cover_reg_top/18.uart_tl_errors.3888540426
/workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3628017600
/workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.609810879
/workspace/coverage/cover_reg_top/19.uart_intr_test.2926641323
/workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2600861387
/workspace/coverage/cover_reg_top/19.uart_tl_errors.3486352931
/workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3697967403
/workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1732103289
/workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.919255579
/workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.505895730
/workspace/coverage/cover_reg_top/2.uart_csr_rw.2223279126
/workspace/coverage/cover_reg_top/2.uart_intr_test.2223770387
/workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2683431713
/workspace/coverage/cover_reg_top/2.uart_tl_errors.2163160460
/workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3631378959
/workspace/coverage/cover_reg_top/20.uart_intr_test.88761278
/workspace/coverage/cover_reg_top/21.uart_intr_test.2372394354
/workspace/coverage/cover_reg_top/22.uart_intr_test.1950949306
/workspace/coverage/cover_reg_top/23.uart_intr_test.3793508357
/workspace/coverage/cover_reg_top/24.uart_intr_test.1877588213
/workspace/coverage/cover_reg_top/25.uart_intr_test.3292470309
/workspace/coverage/cover_reg_top/26.uart_intr_test.2409204178
/workspace/coverage/cover_reg_top/27.uart_intr_test.579695256
/workspace/coverage/cover_reg_top/28.uart_intr_test.2270188117
/workspace/coverage/cover_reg_top/29.uart_intr_test.2012243245
/workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3096230180
/workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3232426843
/workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2709028502
/workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1346465600
/workspace/coverage/cover_reg_top/3.uart_csr_rw.927378709
/workspace/coverage/cover_reg_top/3.uart_intr_test.2178134435
/workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2663712898
/workspace/coverage/cover_reg_top/3.uart_tl_errors.3599038789
/workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2148482377
/workspace/coverage/cover_reg_top/30.uart_intr_test.4150889853
/workspace/coverage/cover_reg_top/31.uart_intr_test.3825652974
/workspace/coverage/cover_reg_top/32.uart_intr_test.1319562571
/workspace/coverage/cover_reg_top/33.uart_intr_test.334320915
/workspace/coverage/cover_reg_top/34.uart_intr_test.76086461
/workspace/coverage/cover_reg_top/35.uart_intr_test.3559349816
/workspace/coverage/cover_reg_top/36.uart_intr_test.3181012549
/workspace/coverage/cover_reg_top/37.uart_intr_test.1343044418
/workspace/coverage/cover_reg_top/38.uart_intr_test.728992687
/workspace/coverage/cover_reg_top/39.uart_intr_test.4226154380
/workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3083455357
/workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3281189562
/workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1467744238
/workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2287212778
/workspace/coverage/cover_reg_top/4.uart_csr_rw.3582510662
/workspace/coverage/cover_reg_top/4.uart_intr_test.3944509122
/workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3066971233
/workspace/coverage/cover_reg_top/4.uart_tl_errors.3473975579
/workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3004988091
/workspace/coverage/cover_reg_top/40.uart_intr_test.1056168924
/workspace/coverage/cover_reg_top/41.uart_intr_test.2566205487
/workspace/coverage/cover_reg_top/42.uart_intr_test.126793279
/workspace/coverage/cover_reg_top/43.uart_intr_test.2638680565
/workspace/coverage/cover_reg_top/44.uart_intr_test.3900902224
/workspace/coverage/cover_reg_top/45.uart_intr_test.2579627255
/workspace/coverage/cover_reg_top/46.uart_intr_test.2959221182
/workspace/coverage/cover_reg_top/47.uart_intr_test.1281038378
/workspace/coverage/cover_reg_top/48.uart_intr_test.1269153943
/workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1362717460
/workspace/coverage/cover_reg_top/5.uart_csr_rw.608867262
/workspace/coverage/cover_reg_top/5.uart_intr_test.3801392804
/workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2123051338
/workspace/coverage/cover_reg_top/5.uart_tl_errors.4099981235
/workspace/coverage/cover_reg_top/5.uart_tl_intg_err.351567142
/workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1145193195
/workspace/coverage/cover_reg_top/6.uart_csr_rw.2242141743
/workspace/coverage/cover_reg_top/6.uart_intr_test.4243836555
/workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2637354035
/workspace/coverage/cover_reg_top/6.uart_tl_errors.1754627860
/workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1928143055
/workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.229147858
/workspace/coverage/cover_reg_top/7.uart_csr_rw.3721165930
/workspace/coverage/cover_reg_top/7.uart_intr_test.4029685214
/workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1985426401
/workspace/coverage/cover_reg_top/7.uart_tl_errors.2015649176
/workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1740723619
/workspace/coverage/cover_reg_top/8.uart_csr_rw.3455515881
/workspace/coverage/cover_reg_top/8.uart_intr_test.1836165667
/workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.4245008268
/workspace/coverage/cover_reg_top/8.uart_tl_errors.2129237684
/workspace/coverage/cover_reg_top/8.uart_tl_intg_err.4221308964
/workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3749009420
/workspace/coverage/cover_reg_top/9.uart_csr_rw.555705768
/workspace/coverage/cover_reg_top/9.uart_intr_test.717530258
/workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.882259070
/workspace/coverage/cover_reg_top/9.uart_tl_errors.3140890897
/workspace/coverage/cover_reg_top/9.uart_tl_intg_err.373149468



Total test records in report: 165
tests.html | tests1.html | tests2.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3960430747 Mar 14 12:19:09 PM PDT 24 Mar 14 12:19:11 PM PDT 24 93887574 ps
T2 /workspace/coverage/cover_reg_top/49.uart_intr_test.3185422127 Mar 14 12:22:12 PM PDT 24 Mar 14 12:22:13 PM PDT 24 25389624 ps
T3 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.882259070 Mar 14 12:20:39 PM PDT 24 Mar 14 12:20:40 PM PDT 24 24268780 ps
T6 /workspace/coverage/cover_reg_top/4.uart_intr_test.3944509122 Mar 14 12:21:20 PM PDT 24 Mar 14 12:21:21 PM PDT 24 119731264 ps
T7 /workspace/coverage/cover_reg_top/19.uart_csr_rw.381627502 Mar 14 12:23:44 PM PDT 24 Mar 14 12:23:46 PM PDT 24 51051701 ps
T4 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3314363626 Mar 14 12:23:34 PM PDT 24 Mar 14 12:23:35 PM PDT 24 92228372 ps
T5 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3815723264 Mar 14 12:19:08 PM PDT 24 Mar 14 12:19:10 PM PDT 24 215155851 ps
T11 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1691023752 Mar 14 12:20:01 PM PDT 24 Mar 14 12:20:02 PM PDT 24 13415916 ps
T12 /workspace/coverage/cover_reg_top/18.uart_tl_errors.3888540426 Mar 14 12:24:20 PM PDT 24 Mar 14 12:24:22 PM PDT 24 123430110 ps
T8 /workspace/coverage/cover_reg_top/21.uart_intr_test.2372394354 Mar 14 12:23:47 PM PDT 24 Mar 14 12:23:49 PM PDT 24 13953864 ps
T13 /workspace/coverage/cover_reg_top/1.uart_tl_errors.39628069 Mar 14 12:20:02 PM PDT 24 Mar 14 12:20:04 PM PDT 24 127559438 ps
T22 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1985426401 Mar 14 12:20:25 PM PDT 24 Mar 14 12:20:26 PM PDT 24 19258311 ps
T29 /workspace/coverage/cover_reg_top/38.uart_intr_test.728992687 Mar 14 12:24:08 PM PDT 24 Mar 14 12:24:09 PM PDT 24 11029876 ps
T10 /workspace/coverage/cover_reg_top/43.uart_intr_test.2638680565 Mar 14 12:23:47 PM PDT 24 Mar 14 12:23:49 PM PDT 24 13573956 ps
T9 /workspace/coverage/cover_reg_top/27.uart_intr_test.579695256 Mar 14 12:24:23 PM PDT 24 Mar 14 12:24:24 PM PDT 24 16887982 ps
T23 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2637354035 Mar 14 12:19:41 PM PDT 24 Mar 14 12:19:42 PM PDT 24 101733139 ps
T14 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1814299948 Mar 14 12:23:34 PM PDT 24 Mar 14 12:23:35 PM PDT 24 127778284 ps
T49 /workspace/coverage/cover_reg_top/46.uart_intr_test.2959221182 Mar 14 12:22:12 PM PDT 24 Mar 14 12:22:13 PM PDT 24 37892621 ps
T15 /workspace/coverage/cover_reg_top/16.uart_tl_errors.56295968 Mar 14 12:24:34 PM PDT 24 Mar 14 12:24:36 PM PDT 24 107261634 ps
T24 /workspace/coverage/cover_reg_top/5.uart_csr_rw.608867262 Mar 14 12:24:08 PM PDT 24 Mar 14 12:24:09 PM PDT 24 12718384 ps
T16 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.609810879 Mar 14 12:23:47 PM PDT 24 Mar 14 12:23:49 PM PDT 24 109813517 ps
T25 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3662637858 Mar 14 12:19:01 PM PDT 24 Mar 14 12:19:02 PM PDT 24 50451178 ps
T51 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3179117802 Mar 14 12:20:03 PM PDT 24 Mar 14 12:20:04 PM PDT 24 51682602 ps
T17 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.229147858 Mar 14 12:19:59 PM PDT 24 Mar 14 12:19:59 PM PDT 24 37604171 ps
T61 /workspace/coverage/cover_reg_top/32.uart_intr_test.1319562571 Mar 14 12:24:01 PM PDT 24 Mar 14 12:24:02 PM PDT 24 46100061 ps
T19 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1362717460 Mar 14 12:19:53 PM PDT 24 Mar 14 12:19:53 PM PDT 24 21447252 ps
T26 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3697967403 Mar 14 12:24:02 PM PDT 24 Mar 14 12:24:03 PM PDT 24 41735230 ps
T18 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1171831102 Mar 14 12:22:27 PM PDT 24 Mar 14 12:22:28 PM PDT 24 304017798 ps
T48 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.919255579 Mar 14 12:19:44 PM PDT 24 Mar 14 12:19:45 PM PDT 24 12335271 ps
T20 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2287212778 Mar 14 12:22:08 PM PDT 24 Mar 14 12:22:09 PM PDT 24 70673549 ps
T45 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.4245008268 Mar 14 12:21:20 PM PDT 24 Mar 14 12:21:22 PM PDT 24 23261476 ps
T54 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2148482377 Mar 14 12:22:27 PM PDT 24 Mar 14 12:22:28 PM PDT 24 176316083 ps
T27 /workspace/coverage/cover_reg_top/14.uart_csr_rw.4006750713 Mar 14 12:18:55 PM PDT 24 Mar 14 12:18:56 PM PDT 24 13578159 ps
T28 /workspace/coverage/cover_reg_top/12.uart_csr_rw.2308147172 Mar 14 12:23:51 PM PDT 24 Mar 14 12:23:52 PM PDT 24 44263049 ps
T21 /workspace/coverage/cover_reg_top/9.uart_tl_errors.3140890897 Mar 14 12:21:42 PM PDT 24 Mar 14 12:21:44 PM PDT 24 211126018 ps
T50 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2709028502 Mar 14 12:23:56 PM PDT 24 Mar 14 12:23:57 PM PDT 24 19346676 ps
T52 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3004988091 Mar 14 12:21:20 PM PDT 24 Mar 14 12:21:22 PM PDT 24 54003304 ps
T46 /workspace/coverage/cover_reg_top/15.uart_csr_rw.4001840582 Mar 14 12:20:01 PM PDT 24 Mar 14 12:20:02 PM PDT 24 144555055 ps
T59 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.587492791 Mar 14 12:21:20 PM PDT 24 Mar 14 12:21:22 PM PDT 24 677526756 ps
T62 /workspace/coverage/cover_reg_top/12.uart_intr_test.3032860243 Mar 14 12:23:25 PM PDT 24 Mar 14 12:23:26 PM PDT 24 40744111 ps
T30 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3096230180 Mar 14 12:24:18 PM PDT 24 Mar 14 12:24:19 PM PDT 24 68563984 ps
T36 /workspace/coverage/cover_reg_top/8.uart_intr_test.1836165667 Mar 14 12:20:29 PM PDT 24 Mar 14 12:20:30 PM PDT 24 52297065 ps
T37 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2456006506 Mar 14 12:18:57 PM PDT 24 Mar 14 12:18:58 PM PDT 24 39273912 ps
T38 /workspace/coverage/cover_reg_top/16.uart_intr_test.3152677276 Mar 14 12:18:55 PM PDT 24 Mar 14 12:18:56 PM PDT 24 13684844 ps
T39 /workspace/coverage/cover_reg_top/17.uart_tl_errors.2167701632 Mar 14 12:23:51 PM PDT 24 Mar 14 12:23:53 PM PDT 24 275956603 ps
T40 /workspace/coverage/cover_reg_top/6.uart_tl_errors.1754627860 Mar 14 12:23:45 PM PDT 24 Mar 14 12:23:48 PM PDT 24 73357167 ps
T41 /workspace/coverage/cover_reg_top/35.uart_intr_test.3559349816 Mar 14 12:24:23 PM PDT 24 Mar 14 12:24:24 PM PDT 24 14006876 ps
T42 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.677520648 Mar 14 12:23:35 PM PDT 24 Mar 14 12:23:36 PM PDT 24 81036730 ps
T43 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1755106807 Mar 14 12:23:48 PM PDT 24 Mar 14 12:23:51 PM PDT 24 57312135 ps
T44 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3631378959 Mar 14 12:24:18 PM PDT 24 Mar 14 12:24:19 PM PDT 24 186205327 ps
T63 /workspace/coverage/cover_reg_top/17.uart_intr_test.2227681596 Mar 14 12:19:09 PM PDT 24 Mar 14 12:19:10 PM PDT 24 12384986 ps
T64 /workspace/coverage/cover_reg_top/10.uart_tl_errors.799417262 Mar 14 12:24:14 PM PDT 24 Mar 14 12:24:15 PM PDT 24 112276278 ps
T65 /workspace/coverage/cover_reg_top/36.uart_intr_test.3181012549 Mar 14 12:19:13 PM PDT 24 Mar 14 12:19:13 PM PDT 24 13468039 ps
T47 /workspace/coverage/cover_reg_top/10.uart_csr_rw.2574776281 Mar 14 12:19:25 PM PDT 24 Mar 14 12:19:25 PM PDT 24 16202778 ps
T66 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.607074045 Mar 14 12:23:50 PM PDT 24 Mar 14 12:23:52 PM PDT 24 25155647 ps
T67 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.4258888228 Mar 14 12:20:57 PM PDT 24 Mar 14 12:20:58 PM PDT 24 60528688 ps
T68 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1740723619 Mar 14 12:22:07 PM PDT 24 Mar 14 12:22:08 PM PDT 24 59960577 ps
T69 /workspace/coverage/cover_reg_top/14.uart_intr_test.3858934866 Mar 14 12:22:37 PM PDT 24 Mar 14 12:22:38 PM PDT 24 14293151 ps
T70 /workspace/coverage/cover_reg_top/42.uart_intr_test.126793279 Mar 14 12:21:15 PM PDT 24 Mar 14 12:21:15 PM PDT 24 16324568 ps
T71 /workspace/coverage/cover_reg_top/25.uart_intr_test.3292470309 Mar 14 12:24:34 PM PDT 24 Mar 14 12:24:35 PM PDT 24 13640860 ps
T72 /workspace/coverage/cover_reg_top/44.uart_intr_test.3900902224 Mar 14 12:23:36 PM PDT 24 Mar 14 12:23:36 PM PDT 24 38621295 ps
T73 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.505895730 Mar 14 12:22:27 PM PDT 24 Mar 14 12:22:28 PM PDT 24 21947282 ps
T74 /workspace/coverage/cover_reg_top/39.uart_intr_test.4226154380 Mar 14 12:23:33 PM PDT 24 Mar 14 12:23:34 PM PDT 24 14197081 ps
T75 /workspace/coverage/cover_reg_top/7.uart_intr_test.4029685214 Mar 14 12:21:12 PM PDT 24 Mar 14 12:21:13 PM PDT 24 106421877 ps
T76 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1346465600 Mar 14 12:21:35 PM PDT 24 Mar 14 12:21:36 PM PDT 24 18550527 ps
T77 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2366137752 Mar 14 12:20:57 PM PDT 24 Mar 14 12:20:58 PM PDT 24 18784017 ps
T78 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2196166742 Mar 14 12:19:08 PM PDT 24 Mar 14 12:19:09 PM PDT 24 48624138 ps
T79 /workspace/coverage/cover_reg_top/6.uart_csr_rw.2242141743 Mar 14 12:24:24 PM PDT 24 Mar 14 12:24:25 PM PDT 24 28376252 ps
T80 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3281189562 Mar 14 12:21:42 PM PDT 24 Mar 14 12:21:45 PM PDT 24 177920350 ps
T81 /workspace/coverage/cover_reg_top/4.uart_csr_rw.3582510662 Mar 14 12:19:10 PM PDT 24 Mar 14 12:19:11 PM PDT 24 13216311 ps
T82 /workspace/coverage/cover_reg_top/13.uart_intr_test.780589201 Mar 14 12:22:02 PM PDT 24 Mar 14 12:22:02 PM PDT 24 16066174 ps
T31 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.541112352 Mar 14 12:21:14 PM PDT 24 Mar 14 12:21:15 PM PDT 24 52382540 ps
T83 /workspace/coverage/cover_reg_top/18.uart_csr_rw.4005589873 Mar 14 12:23:44 PM PDT 24 Mar 14 12:23:46 PM PDT 24 60628309 ps
T84 /workspace/coverage/cover_reg_top/5.uart_intr_test.3801392804 Mar 14 12:19:49 PM PDT 24 Mar 14 12:19:50 PM PDT 24 110641587 ps
T85 /workspace/coverage/cover_reg_top/34.uart_intr_test.76086461 Mar 14 12:24:08 PM PDT 24 Mar 14 12:24:09 PM PDT 24 22390874 ps
T86 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3749009420 Mar 14 12:20:20 PM PDT 24 Mar 14 12:20:21 PM PDT 24 32055703 ps
T87 /workspace/coverage/cover_reg_top/11.uart_intr_test.2163221471 Mar 14 12:23:45 PM PDT 24 Mar 14 12:23:47 PM PDT 24 16137422 ps
T53 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1928143055 Mar 14 12:20:19 PM PDT 24 Mar 14 12:20:20 PM PDT 24 387816844 ps
T88 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3382411560 Mar 14 12:23:25 PM PDT 24 Mar 14 12:23:27 PM PDT 24 18686309 ps
T89 /workspace/coverage/cover_reg_top/16.uart_csr_rw.2705591098 Mar 14 12:24:34 PM PDT 24 Mar 14 12:24:35 PM PDT 24 36605694 ps
T90 /workspace/coverage/cover_reg_top/29.uart_intr_test.2012243245 Mar 14 12:22:42 PM PDT 24 Mar 14 12:22:43 PM PDT 24 129509786 ps
T91 /workspace/coverage/cover_reg_top/18.uart_intr_test.615998439 Mar 14 12:23:33 PM PDT 24 Mar 14 12:23:34 PM PDT 24 29256512 ps
T92 /workspace/coverage/cover_reg_top/2.uart_tl_errors.2163160460 Mar 14 12:21:42 PM PDT 24 Mar 14 12:21:44 PM PDT 24 1232290082 ps
T93 /workspace/coverage/cover_reg_top/1.uart_csr_rw.2232036081 Mar 14 12:19:00 PM PDT 24 Mar 14 12:19:01 PM PDT 24 13240660 ps
T94 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1377173604 Mar 14 12:23:34 PM PDT 24 Mar 14 12:23:34 PM PDT 24 41412055 ps
T95 /workspace/coverage/cover_reg_top/37.uart_intr_test.1343044418 Mar 14 12:19:09 PM PDT 24 Mar 14 12:19:10 PM PDT 24 14262841 ps
T96 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3056986023 Mar 14 12:24:23 PM PDT 24 Mar 14 12:24:24 PM PDT 24 58690810 ps
T97 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1072459655 Mar 14 12:23:46 PM PDT 24 Mar 14 12:23:48 PM PDT 24 86338666 ps
T98 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2663712898 Mar 14 12:20:01 PM PDT 24 Mar 14 12:20:02 PM PDT 24 18998851 ps
T99 /workspace/coverage/cover_reg_top/40.uart_intr_test.1056168924 Mar 14 12:19:22 PM PDT 24 Mar 14 12:19:23 PM PDT 24 13879334 ps
T100 /workspace/coverage/cover_reg_top/14.uart_tl_errors.1020425653 Mar 14 12:23:34 PM PDT 24 Mar 14 12:23:36 PM PDT 24 391963272 ps
T101 /workspace/coverage/cover_reg_top/28.uart_intr_test.2270188117 Mar 14 12:21:41 PM PDT 24 Mar 14 12:21:42 PM PDT 24 18208704 ps
T102 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1145193195 Mar 14 12:19:45 PM PDT 24 Mar 14 12:19:47 PM PDT 24 22150554 ps
T103 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.133940991 Mar 14 12:23:33 PM PDT 24 Mar 14 12:23:34 PM PDT 24 41927250 ps
T104 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.728562490 Mar 14 12:19:36 PM PDT 24 Mar 14 12:19:38 PM PDT 24 435721272 ps
T57 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.373149468 Mar 14 12:21:22 PM PDT 24 Mar 14 12:21:23 PM PDT 24 162893367 ps
T105 /workspace/coverage/cover_reg_top/3.uart_tl_errors.3599038789 Mar 14 12:19:49 PM PDT 24 Mar 14 12:19:50 PM PDT 24 49883684 ps
T106 /workspace/coverage/cover_reg_top/20.uart_intr_test.88761278 Mar 14 12:24:20 PM PDT 24 Mar 14 12:24:21 PM PDT 24 10945990 ps
T107 /workspace/coverage/cover_reg_top/26.uart_intr_test.2409204178 Mar 14 12:24:20 PM PDT 24 Mar 14 12:24:21 PM PDT 24 59736339 ps
T108 /workspace/coverage/cover_reg_top/31.uart_intr_test.3825652974 Mar 14 12:22:42 PM PDT 24 Mar 14 12:22:43 PM PDT 24 14562444 ps
T109 /workspace/coverage/cover_reg_top/1.uart_intr_test.2321315190 Mar 14 12:22:05 PM PDT 24 Mar 14 12:22:06 PM PDT 24 39063355 ps
T110 /workspace/coverage/cover_reg_top/8.uart_tl_errors.2129237684 Mar 14 12:24:02 PM PDT 24 Mar 14 12:24:03 PM PDT 24 19116916 ps
T111 /workspace/coverage/cover_reg_top/6.uart_intr_test.4243836555 Mar 14 12:19:22 PM PDT 24 Mar 14 12:19:23 PM PDT 24 33194616 ps
T112 /workspace/coverage/cover_reg_top/24.uart_intr_test.1877588213 Mar 14 12:24:20 PM PDT 24 Mar 14 12:24:21 PM PDT 24 103249996 ps
T113 /workspace/coverage/cover_reg_top/19.uart_intr_test.2926641323 Mar 14 12:23:45 PM PDT 24 Mar 14 12:23:47 PM PDT 24 101112455 ps
T114 /workspace/coverage/cover_reg_top/19.uart_tl_errors.3486352931 Mar 14 12:23:34 PM PDT 24 Mar 14 12:23:36 PM PDT 24 17185006 ps
T115 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.880107079 Mar 14 12:21:46 PM PDT 24 Mar 14 12:21:48 PM PDT 24 200832580 ps
T116 /workspace/coverage/cover_reg_top/4.uart_tl_errors.3473975579 Mar 14 12:19:04 PM PDT 24 Mar 14 12:19:06 PM PDT 24 50509283 ps
T117 /workspace/coverage/cover_reg_top/17.uart_csr_rw.1673693742 Mar 14 12:23:48 PM PDT 24 Mar 14 12:23:49 PM PDT 24 49475461 ps
T118 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.4221308964 Mar 14 12:20:12 PM PDT 24 Mar 14 12:20:13 PM PDT 24 42597885 ps
T119 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2123051338 Mar 14 12:21:00 PM PDT 24 Mar 14 12:21:01 PM PDT 24 24051973 ps
T120 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3232426843 Mar 14 12:19:01 PM PDT 24 Mar 14 12:19:02 PM PDT 24 155491122 ps
T121 /workspace/coverage/cover_reg_top/0.uart_csr_rw.875125490 Mar 14 12:21:29 PM PDT 24 Mar 14 12:21:29 PM PDT 24 76125529 ps
T122 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.662298781 Mar 14 12:23:46 PM PDT 24 Mar 14 12:23:50 PM PDT 24 68240772 ps
T123 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2357129875 Mar 14 12:19:00 PM PDT 24 Mar 14 12:19:02 PM PDT 24 84270667 ps
T124 /workspace/coverage/cover_reg_top/23.uart_intr_test.3793508357 Mar 14 12:21:51 PM PDT 24 Mar 14 12:21:51 PM PDT 24 53142530 ps
T125 /workspace/coverage/cover_reg_top/41.uart_intr_test.2566205487 Mar 14 12:19:00 PM PDT 24 Mar 14 12:19:01 PM PDT 24 13142524 ps
T126 /workspace/coverage/cover_reg_top/2.uart_intr_test.2223770387 Mar 14 12:23:29 PM PDT 24 Mar 14 12:23:29 PM PDT 24 15540603 ps
T127 /workspace/coverage/cover_reg_top/0.uart_intr_test.1909214533 Mar 14 12:24:08 PM PDT 24 Mar 14 12:24:09 PM PDT 24 42929520 ps
T128 /workspace/coverage/cover_reg_top/11.uart_tl_errors.2129561948 Mar 14 12:20:34 PM PDT 24 Mar 14 12:20:37 PM PDT 24 216537854 ps
T129 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.837978320 Mar 14 12:22:00 PM PDT 24 Mar 14 12:22:01 PM PDT 24 28996734 ps
T60 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3628017600 Mar 14 12:23:44 PM PDT 24 Mar 14 12:23:46 PM PDT 24 307574492 ps
T130 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2336824163 Mar 14 12:19:02 PM PDT 24 Mar 14 12:19:03 PM PDT 24 55970097 ps
T55 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.438356927 Mar 14 12:24:23 PM PDT 24 Mar 14 12:24:25 PM PDT 24 93293082 ps
T131 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3066971233 Mar 14 12:19:59 PM PDT 24 Mar 14 12:20:00 PM PDT 24 167486878 ps
T132 /workspace/coverage/cover_reg_top/47.uart_intr_test.1281038378 Mar 14 12:21:14 PM PDT 24 Mar 14 12:21:15 PM PDT 24 27316924 ps
T32 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3083455357 Mar 14 12:19:47 PM PDT 24 Mar 14 12:19:48 PM PDT 24 50030634 ps
T133 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1827427779 Mar 14 12:23:26 PM PDT 24 Mar 14 12:23:27 PM PDT 24 36974891 ps
T58 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1315331533 Mar 14 12:22:16 PM PDT 24 Mar 14 12:22:18 PM PDT 24 46023338 ps
T56 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.398847603 Mar 14 12:24:22 PM PDT 24 Mar 14 12:24:24 PM PDT 24 95619958 ps
T134 /workspace/coverage/cover_reg_top/2.uart_csr_rw.2223279126 Mar 14 12:24:18 PM PDT 24 Mar 14 12:24:19 PM PDT 24 42106159 ps
T135 /workspace/coverage/cover_reg_top/13.uart_csr_rw.2211324484 Mar 14 12:23:48 PM PDT 24 Mar 14 12:23:50 PM PDT 24 47241652 ps
T136 /workspace/coverage/cover_reg_top/7.uart_csr_rw.3721165930 Mar 14 12:20:12 PM PDT 24 Mar 14 12:20:13 PM PDT 24 42696114 ps
T137 /workspace/coverage/cover_reg_top/3.uart_intr_test.2178134435 Mar 14 12:21:45 PM PDT 24 Mar 14 12:21:46 PM PDT 24 134954117 ps
T138 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1843969761 Mar 14 12:22:05 PM PDT 24 Mar 14 12:22:06 PM PDT 24 22709827 ps
T139 /workspace/coverage/cover_reg_top/8.uart_csr_rw.3455515881 Mar 14 12:19:59 PM PDT 24 Mar 14 12:20:00 PM PDT 24 45137127 ps
T140 /workspace/coverage/cover_reg_top/10.uart_intr_test.720116138 Mar 14 12:20:19 PM PDT 24 Mar 14 12:20:20 PM PDT 24 32173626 ps
T141 /workspace/coverage/cover_reg_top/15.uart_tl_errors.3470074301 Mar 14 12:23:31 PM PDT 24 Mar 14 12:23:33 PM PDT 24 251404033 ps
T142 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.351567142 Mar 14 12:19:59 PM PDT 24 Mar 14 12:20:00 PM PDT 24 42103209 ps
T143 /workspace/coverage/cover_reg_top/30.uart_intr_test.4150889853 Mar 14 12:21:45 PM PDT 24 Mar 14 12:21:46 PM PDT 24 42286314 ps
T144 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2421035005 Mar 14 12:22:25 PM PDT 24 Mar 14 12:22:26 PM PDT 24 18639578 ps
T145 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2243330089 Mar 14 12:23:44 PM PDT 24 Mar 14 12:23:46 PM PDT 24 83345433 ps
T146 /workspace/coverage/cover_reg_top/9.uart_intr_test.717530258 Mar 14 12:24:15 PM PDT 24 Mar 14 12:24:15 PM PDT 24 13258084 ps
T147 /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1467744238 Mar 14 12:24:02 PM PDT 24 Mar 14 12:24:03 PM PDT 24 13335819 ps
T148 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2683431713 Mar 14 12:18:54 PM PDT 24 Mar 14 12:18:55 PM PDT 24 21452315 ps
T149 /workspace/coverage/cover_reg_top/33.uart_intr_test.334320915 Mar 14 12:24:26 PM PDT 24 Mar 14 12:24:27 PM PDT 24 14213144 ps
T150 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1617121748 Mar 14 12:18:40 PM PDT 24 Mar 14 12:18:41 PM PDT 24 52554197 ps
T151 /workspace/coverage/cover_reg_top/48.uart_intr_test.1269153943 Mar 14 12:23:33 PM PDT 24 Mar 14 12:23:34 PM PDT 24 39665186 ps
T152 /workspace/coverage/cover_reg_top/22.uart_intr_test.1950949306 Mar 14 12:24:28 PM PDT 24 Mar 14 12:24:29 PM PDT 24 27533074 ps
T153 /workspace/coverage/cover_reg_top/45.uart_intr_test.2579627255 Mar 14 12:21:14 PM PDT 24 Mar 14 12:21:15 PM PDT 24 21594845 ps
T33 /workspace/coverage/cover_reg_top/9.uart_csr_rw.555705768 Mar 14 12:24:24 PM PDT 24 Mar 14 12:24:25 PM PDT 24 40217346 ps
T154 /workspace/coverage/cover_reg_top/0.uart_tl_errors.1381947347 Mar 14 12:19:49 PM PDT 24 Mar 14 12:19:51 PM PDT 24 118328810 ps
T155 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1732103289 Mar 14 12:23:40 PM PDT 24 Mar 14 12:23:42 PM PDT 24 234443568 ps
T156 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2600861387 Mar 14 12:23:47 PM PDT 24 Mar 14 12:23:50 PM PDT 24 256866175 ps
T35 /workspace/coverage/cover_reg_top/11.uart_csr_rw.2537228290 Mar 14 12:24:15 PM PDT 24 Mar 14 12:24:15 PM PDT 24 22007067 ps
T157 /workspace/coverage/cover_reg_top/15.uart_intr_test.2658162695 Mar 14 12:23:56 PM PDT 24 Mar 14 12:23:56 PM PDT 24 102462717 ps
T158 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.4089707481 Mar 14 12:23:29 PM PDT 24 Mar 14 12:23:31 PM PDT 24 386022454 ps
T159 /workspace/coverage/cover_reg_top/13.uart_tl_errors.2261684345 Mar 14 12:23:35 PM PDT 24 Mar 14 12:23:37 PM PDT 24 128107593 ps
T160 /workspace/coverage/cover_reg_top/3.uart_csr_rw.927378709 Mar 14 12:23:39 PM PDT 24 Mar 14 12:23:40 PM PDT 24 69979649 ps
T161 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1761546948 Mar 14 12:20:01 PM PDT 24 Mar 14 12:20:02 PM PDT 24 97421968 ps
T162 /workspace/coverage/cover_reg_top/7.uart_tl_errors.2015649176 Mar 14 12:20:18 PM PDT 24 Mar 14 12:20:20 PM PDT 24 109482743 ps
T163 /workspace/coverage/cover_reg_top/5.uart_tl_errors.4099981235 Mar 14 12:19:09 PM PDT 24 Mar 14 12:19:11 PM PDT 24 120185507 ps
T164 /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3682071287 Mar 14 12:18:49 PM PDT 24 Mar 14 12:18:51 PM PDT 24 135348455 ps
T34 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2242492548 Mar 14 12:21:34 PM PDT 24 Mar 14 12:21:35 PM PDT 24 53499282 ps
T165 /workspace/coverage/cover_reg_top/12.uart_tl_errors.483065321 Mar 14 12:20:03 PM PDT 24 Mar 14 12:20:05 PM PDT 24 36103762 ps

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3314363626
Short name T4
Test name
Test status
Simulation time 92228372 ps
CPU time 1.33 seconds
Started Mar 14 12:23:34 PM PDT 24
Finished Mar 14 12:23:35 PM PDT 24
Peak memory 199664 kb
Host smart-d789eb58-90f4-456f-b5cb-cc613098a9fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314363626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3314363626
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3185422127
Short name T2
Test name
Test status
Simulation time 25389624 ps
CPU time 0.59 seconds
Started Mar 14 12:22:12 PM PDT 24
Finished Mar 14 12:22:13 PM PDT 24
Peak memory 195076 kb
Host smart-da09be75-9a95-443f-9082-38e3780a1ef0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185422127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3185422127
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.39628069
Short name T13
Test name
Test status
Simulation time 127559438 ps
CPU time 2.81 seconds
Started Mar 14 12:20:02 PM PDT 24
Finished Mar 14 12:20:04 PM PDT 24
Peak memory 200672 kb
Host smart-86761919-55a2-49a8-a159-64342b38e536
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39628069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.39628069
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1691023752
Short name T11
Test name
Test status
Simulation time 13415916 ps
CPU time 0.58 seconds
Started Mar 14 12:20:01 PM PDT 24
Finished Mar 14 12:20:02 PM PDT 24
Peak memory 195928 kb
Host smart-64d6fa41-f1da-467f-b2c2-b86add8423eb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691023752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1691023752
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.381627502
Short name T7
Test name
Test status
Simulation time 51051701 ps
CPU time 0.65 seconds
Started Mar 14 12:23:44 PM PDT 24
Finished Mar 14 12:23:46 PM PDT 24
Peak memory 194664 kb
Host smart-fe1df032-4a24-4106-9099-e064b619d552
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381627502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.381627502
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2242492548
Short name T34
Test name
Test status
Simulation time 53499282 ps
CPU time 0.79 seconds
Started Mar 14 12:21:34 PM PDT 24
Finished Mar 14 12:21:35 PM PDT 24
Peak memory 196952 kb
Host smart-b393a786-4926-46b4-9397-ddc5220f3085
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242492548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2242492548
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.3152677276
Short name T38
Test name
Test status
Simulation time 13684844 ps
CPU time 0.59 seconds
Started Mar 14 12:18:55 PM PDT 24
Finished Mar 14 12:18:56 PM PDT 24
Peak memory 194948 kb
Host smart-767cc155-b3c7-44af-b44a-f32f912eb1e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152677276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3152677276
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.4089707481
Short name T158
Test name
Test status
Simulation time 386022454 ps
CPU time 0.96 seconds
Started Mar 14 12:23:29 PM PDT 24
Finished Mar 14 12:23:31 PM PDT 24
Peak memory 199316 kb
Host smart-141f6b09-6933-422d-a2ae-7ea05c328b05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089707481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.4089707481
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.587492791
Short name T59
Test name
Test status
Simulation time 677526756 ps
CPU time 1.47 seconds
Started Mar 14 12:21:20 PM PDT 24
Finished Mar 14 12:21:22 PM PDT 24
Peak memory 199880 kb
Host smart-d295bc6d-9967-4d9f-a50a-a4e97325389e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587492791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.587492791
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1315331533
Short name T58
Test name
Test status
Simulation time 46023338 ps
CPU time 0.98 seconds
Started Mar 14 12:22:16 PM PDT 24
Finished Mar 14 12:22:18 PM PDT 24
Peak memory 199696 kb
Host smart-864e9dbf-6b60-4594-9409-3d0bf2968116
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315331533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1315331533
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3032860243
Short name T62
Test name
Test status
Simulation time 40744111 ps
CPU time 0.65 seconds
Started Mar 14 12:23:25 PM PDT 24
Finished Mar 14 12:23:26 PM PDT 24
Peak memory 193712 kb
Host smart-93f528a5-a690-4deb-9d69-ce3cf805b50c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032860243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3032860243
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.728562490
Short name T104
Test name
Test status
Simulation time 435721272 ps
CPU time 2.56 seconds
Started Mar 14 12:19:36 PM PDT 24
Finished Mar 14 12:19:38 PM PDT 24
Peak memory 197980 kb
Host smart-d7f9f6d3-9fdb-4b6c-befa-4a24307231ea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728562490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.728562490
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1843969761
Short name T138
Test name
Test status
Simulation time 22709827 ps
CPU time 0.71 seconds
Started Mar 14 12:22:05 PM PDT 24
Finished Mar 14 12:22:06 PM PDT 24
Peak memory 198828 kb
Host smart-a033e1e4-9fa2-4389-ac91-d03a27bc953c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843969761 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1843969761
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.875125490
Short name T121
Test name
Test status
Simulation time 76125529 ps
CPU time 0.63 seconds
Started Mar 14 12:21:29 PM PDT 24
Finished Mar 14 12:21:29 PM PDT 24
Peak memory 196036 kb
Host smart-3c316751-677c-4e06-8970-c71b517e0908
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875125490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.875125490
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1909214533
Short name T127
Test name
Test status
Simulation time 42929520 ps
CPU time 0.61 seconds
Started Mar 14 12:24:08 PM PDT 24
Finished Mar 14 12:24:09 PM PDT 24
Peak memory 193852 kb
Host smart-3fe3d82b-52d9-4f65-bbb0-548ed10184fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909214533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1909214533
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1827427779
Short name T133
Test name
Test status
Simulation time 36974891 ps
CPU time 0.8 seconds
Started Mar 14 12:23:26 PM PDT 24
Finished Mar 14 12:23:27 PM PDT 24
Peak memory 198264 kb
Host smart-95ff9562-46bd-4dab-88e4-97f99eb07c22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827427779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1827427779
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.1381947347
Short name T154
Test name
Test status
Simulation time 118328810 ps
CPU time 1.46 seconds
Started Mar 14 12:19:49 PM PDT 24
Finished Mar 14 12:19:51 PM PDT 24
Peak memory 200672 kb
Host smart-69a76158-9e31-4001-9951-ad89eb1601f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381947347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.1381947347
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3179117802
Short name T51
Test name
Test status
Simulation time 51682602 ps
CPU time 1.06 seconds
Started Mar 14 12:20:03 PM PDT 24
Finished Mar 14 12:20:04 PM PDT 24
Peak memory 199784 kb
Host smart-ee647c80-49f2-4c5c-a797-3e4a634079fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179117802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3179117802
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.541112352
Short name T31
Test name
Test status
Simulation time 52382540 ps
CPU time 0.8 seconds
Started Mar 14 12:21:14 PM PDT 24
Finished Mar 14 12:21:15 PM PDT 24
Peak memory 197132 kb
Host smart-968d2398-dcf9-4143-ae17-2c4019014f00
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541112352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.541112352
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.3682071287
Short name T164
Test name
Test status
Simulation time 135348455 ps
CPU time 1.62 seconds
Started Mar 14 12:18:49 PM PDT 24
Finished Mar 14 12:18:51 PM PDT 24
Peak memory 198000 kb
Host smart-dee9738d-35af-40af-a3bb-86af8a465ead
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682071287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.3682071287
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1617121748
Short name T150
Test name
Test status
Simulation time 52554197 ps
CPU time 0.59 seconds
Started Mar 14 12:18:40 PM PDT 24
Finished Mar 14 12:18:41 PM PDT 24
Peak memory 196424 kb
Host smart-807abe74-9542-4625-ad84-9b738f0f7437
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617121748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1617121748
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3960430747
Short name T1
Test name
Test status
Simulation time 93887574 ps
CPU time 1.3 seconds
Started Mar 14 12:19:09 PM PDT 24
Finished Mar 14 12:19:11 PM PDT 24
Peak memory 200484 kb
Host smart-8f96ae82-be21-4d94-a72e-0fc49c430972
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960430747 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3960430747
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2232036081
Short name T93
Test name
Test status
Simulation time 13240660 ps
CPU time 0.58 seconds
Started Mar 14 12:19:00 PM PDT 24
Finished Mar 14 12:19:01 PM PDT 24
Peak memory 195956 kb
Host smart-900dad8b-a36b-43ed-8832-64828a4f0e33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232036081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2232036081
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2321315190
Short name T109
Test name
Test status
Simulation time 39063355 ps
CPU time 0.58 seconds
Started Mar 14 12:22:05 PM PDT 24
Finished Mar 14 12:22:06 PM PDT 24
Peak memory 194992 kb
Host smart-76ab1ca9-f4fb-462e-943d-c5ebd2451362
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321315190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2321315190
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2366137752
Short name T77
Test name
Test status
Simulation time 18784017 ps
CPU time 0.79 seconds
Started Mar 14 12:20:57 PM PDT 24
Finished Mar 14 12:20:58 PM PDT 24
Peak memory 197804 kb
Host smart-d7413c0d-32b3-4e6a-b07e-8f6bf18a148d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366137752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2366137752
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2357129875
Short name T123
Test name
Test status
Simulation time 84270667 ps
CPU time 1.35 seconds
Started Mar 14 12:19:00 PM PDT 24
Finished Mar 14 12:19:02 PM PDT 24
Peak memory 200056 kb
Host smart-859f5da5-0f6c-4905-99f9-1497751e8748
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357129875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2357129875
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1072459655
Short name T97
Test name
Test status
Simulation time 86338666 ps
CPU time 0.78 seconds
Started Mar 14 12:23:46 PM PDT 24
Finished Mar 14 12:23:48 PM PDT 24
Peak memory 200216 kb
Host smart-1fe1900e-5a54-4cdb-8db9-4681981ed1d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072459655 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1072459655
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2574776281
Short name T47
Test name
Test status
Simulation time 16202778 ps
CPU time 0.63 seconds
Started Mar 14 12:19:25 PM PDT 24
Finished Mar 14 12:19:25 PM PDT 24
Peak memory 195960 kb
Host smart-82348de5-06bc-4802-947b-6e54a2760554
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574776281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2574776281
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.720116138
Short name T140
Test name
Test status
Simulation time 32173626 ps
CPU time 0.61 seconds
Started Mar 14 12:20:19 PM PDT 24
Finished Mar 14 12:20:20 PM PDT 24
Peak memory 195132 kb
Host smart-4affb042-ab48-49a5-9ee8-41f406aa4e96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720116138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.720116138
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.837978320
Short name T129
Test name
Test status
Simulation time 28996734 ps
CPU time 0.78 seconds
Started Mar 14 12:22:00 PM PDT 24
Finished Mar 14 12:22:01 PM PDT 24
Peak memory 197800 kb
Host smart-05e388a1-45cc-456f-9eb3-24f25f383394
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837978320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr
_outstanding.837978320
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.799417262
Short name T64
Test name
Test status
Simulation time 112276278 ps
CPU time 1.41 seconds
Started Mar 14 12:24:14 PM PDT 24
Finished Mar 14 12:24:15 PM PDT 24
Peak memory 200456 kb
Host smart-e97c4d76-326d-4166-979b-831e25821520
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799417262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.799417262
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.677520648
Short name T42
Test name
Test status
Simulation time 81036730 ps
CPU time 0.74 seconds
Started Mar 14 12:23:35 PM PDT 24
Finished Mar 14 12:23:36 PM PDT 24
Peak memory 197160 kb
Host smart-24e49ec6-0907-4c49-a34a-f65ac8bbdec9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677520648 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.677520648
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2537228290
Short name T35
Test name
Test status
Simulation time 22007067 ps
CPU time 0.57 seconds
Started Mar 14 12:24:15 PM PDT 24
Finished Mar 14 12:24:15 PM PDT 24
Peak memory 196016 kb
Host smart-e7b74f11-3588-4ee1-a806-ad1e2624cd85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537228290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2537228290
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2163221471
Short name T87
Test name
Test status
Simulation time 16137422 ps
CPU time 0.6 seconds
Started Mar 14 12:23:45 PM PDT 24
Finished Mar 14 12:23:47 PM PDT 24
Peak memory 193696 kb
Host smart-ca9dc1ae-34a3-475a-9ada-5332ac237617
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163221471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2163221471
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1377173604
Short name T94
Test name
Test status
Simulation time 41412055 ps
CPU time 0.67 seconds
Started Mar 14 12:23:34 PM PDT 24
Finished Mar 14 12:23:34 PM PDT 24
Peak memory 198396 kb
Host smart-ec61bb66-e2d2-472b-a6ee-f4858b46ca2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377173604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1377173604
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.2129561948
Short name T128
Test name
Test status
Simulation time 216537854 ps
CPU time 2.4 seconds
Started Mar 14 12:20:34 PM PDT 24
Finished Mar 14 12:20:37 PM PDT 24
Peak memory 200680 kb
Host smart-497e2243-2bfc-4b7b-ad72-f540aea5e4e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129561948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2129561948
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1171831102
Short name T18
Test name
Test status
Simulation time 304017798 ps
CPU time 1.27 seconds
Started Mar 14 12:22:27 PM PDT 24
Finished Mar 14 12:22:28 PM PDT 24
Peak memory 199696 kb
Host smart-2bd2c635-949e-4518-81b3-7326fcb6d941
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171831102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1171831102
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.607074045
Short name T66
Test name
Test status
Simulation time 25155647 ps
CPU time 0.72 seconds
Started Mar 14 12:23:50 PM PDT 24
Finished Mar 14 12:23:52 PM PDT 24
Peak memory 199292 kb
Host smart-7cb93460-f15b-4b86-ba7e-96cdb6bba8b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607074045 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.607074045
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2308147172
Short name T28
Test name
Test status
Simulation time 44263049 ps
CPU time 0.58 seconds
Started Mar 14 12:23:51 PM PDT 24
Finished Mar 14 12:23:52 PM PDT 24
Peak memory 195992 kb
Host smart-59315866-6fff-49d2-af90-82995da5cb39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308147172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2308147172
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3382411560
Short name T88
Test name
Test status
Simulation time 18686309 ps
CPU time 0.83 seconds
Started Mar 14 12:23:25 PM PDT 24
Finished Mar 14 12:23:27 PM PDT 24
Peak memory 195936 kb
Host smart-570a2bb3-e4bd-48cf-a0ff-e12ec867d8e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382411560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3382411560
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.483065321
Short name T165
Test name
Test status
Simulation time 36103762 ps
CPU time 1.85 seconds
Started Mar 14 12:20:03 PM PDT 24
Finished Mar 14 12:20:05 PM PDT 24
Peak memory 200676 kb
Host smart-c7dbd069-661f-4dd2-a49d-4b469bd1b8ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483065321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.483065321
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1814299948
Short name T14
Test name
Test status
Simulation time 127778284 ps
CPU time 0.85 seconds
Started Mar 14 12:23:34 PM PDT 24
Finished Mar 14 12:23:35 PM PDT 24
Peak memory 200440 kb
Host smart-de0f3fa0-8da6-444d-97b7-aa326fe83cac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814299948 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.1814299948
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.2211324484
Short name T135
Test name
Test status
Simulation time 47241652 ps
CPU time 0.58 seconds
Started Mar 14 12:23:48 PM PDT 24
Finished Mar 14 12:23:50 PM PDT 24
Peak memory 195376 kb
Host smart-22d4da6c-7b2d-427b-a9ae-8aab6d25c272
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211324484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2211324484
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.780589201
Short name T82
Test name
Test status
Simulation time 16066174 ps
CPU time 0.59 seconds
Started Mar 14 12:22:02 PM PDT 24
Finished Mar 14 12:22:02 PM PDT 24
Peak memory 195028 kb
Host smart-2c690317-8b87-4c05-8326-85067f31c692
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780589201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.780589201
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.662298781
Short name T122
Test name
Test status
Simulation time 68240772 ps
CPU time 0.67 seconds
Started Mar 14 12:23:46 PM PDT 24
Finished Mar 14 12:23:50 PM PDT 24
Peak memory 194644 kb
Host smart-a199959d-b411-4916-a7c1-a8707160da16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662298781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.662298781
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.2261684345
Short name T159
Test name
Test status
Simulation time 128107593 ps
CPU time 1.95 seconds
Started Mar 14 12:23:35 PM PDT 24
Finished Mar 14 12:23:37 PM PDT 24
Peak memory 198860 kb
Host smart-56831815-24bf-4c94-b056-8e2bd07fea16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261684345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.2261684345
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.880107079
Short name T115
Test name
Test status
Simulation time 200832580 ps
CPU time 0.95 seconds
Started Mar 14 12:21:46 PM PDT 24
Finished Mar 14 12:21:48 PM PDT 24
Peak memory 199780 kb
Host smart-cf3c6522-2aa2-4dfe-b96d-a0b1992eaca9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880107079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.880107079
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2421035005
Short name T144
Test name
Test status
Simulation time 18639578 ps
CPU time 0.9 seconds
Started Mar 14 12:22:25 PM PDT 24
Finished Mar 14 12:22:26 PM PDT 24
Peak memory 200356 kb
Host smart-bfe0019f-4b82-4a9f-aedb-8cff18ce4e15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421035005 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2421035005
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.4006750713
Short name T27
Test name
Test status
Simulation time 13578159 ps
CPU time 0.61 seconds
Started Mar 14 12:18:55 PM PDT 24
Finished Mar 14 12:18:56 PM PDT 24
Peak memory 196228 kb
Host smart-797cd6e7-9867-4cbb-b44a-b1679fa086d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006750713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.4006750713
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.3858934866
Short name T69
Test name
Test status
Simulation time 14293151 ps
CPU time 0.64 seconds
Started Mar 14 12:22:37 PM PDT 24
Finished Mar 14 12:22:38 PM PDT 24
Peak memory 195016 kb
Host smart-4d866667-a4d9-4c6d-aae3-7b36f9cfaee8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858934866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3858934866
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3662637858
Short name T25
Test name
Test status
Simulation time 50451178 ps
CPU time 0.67 seconds
Started Mar 14 12:19:01 PM PDT 24
Finished Mar 14 12:19:02 PM PDT 24
Peak memory 196680 kb
Host smart-4755a72d-de91-4b3d-92d0-a0949106850f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662637858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.3662637858
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1020425653
Short name T100
Test name
Test status
Simulation time 391963272 ps
CPU time 1.91 seconds
Started Mar 14 12:23:34 PM PDT 24
Finished Mar 14 12:23:36 PM PDT 24
Peak memory 200612 kb
Host smart-1b46a346-7a1a-43c4-939a-e0e18d0243ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020425653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1020425653
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.398847603
Short name T56
Test name
Test status
Simulation time 95619958 ps
CPU time 1.31 seconds
Started Mar 14 12:24:22 PM PDT 24
Finished Mar 14 12:24:24 PM PDT 24
Peak memory 199992 kb
Host smart-99e9bc17-b8c0-49a7-a7cd-a3e8807f381d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398847603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.398847603
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2456006506
Short name T37
Test name
Test status
Simulation time 39273912 ps
CPU time 0.79 seconds
Started Mar 14 12:18:57 PM PDT 24
Finished Mar 14 12:18:58 PM PDT 24
Peak memory 199680 kb
Host smart-f9cbb613-9170-4441-8b61-2c0bd4c9a14c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456006506 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2456006506
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.4001840582
Short name T46
Test name
Test status
Simulation time 144555055 ps
CPU time 0.58 seconds
Started Mar 14 12:20:01 PM PDT 24
Finished Mar 14 12:20:02 PM PDT 24
Peak memory 195928 kb
Host smart-47fdb197-f492-401c-a9b6-0730bd630ee0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001840582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.4001840582
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2658162695
Short name T157
Test name
Test status
Simulation time 102462717 ps
CPU time 0.59 seconds
Started Mar 14 12:23:56 PM PDT 24
Finished Mar 14 12:23:56 PM PDT 24
Peak memory 194996 kb
Host smart-dc1baff3-5736-4019-bcc9-077b8281e866
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658162695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2658162695
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.4258888228
Short name T67
Test name
Test status
Simulation time 60528688 ps
CPU time 0.78 seconds
Started Mar 14 12:20:57 PM PDT 24
Finished Mar 14 12:20:58 PM PDT 24
Peak memory 196296 kb
Host smart-2f45ded5-50c0-4625-b950-d2d9720692b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258888228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.4258888228
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.3470074301
Short name T141
Test name
Test status
Simulation time 251404033 ps
CPU time 1.61 seconds
Started Mar 14 12:23:31 PM PDT 24
Finished Mar 14 12:23:33 PM PDT 24
Peak memory 199500 kb
Host smart-5bda0f03-5afe-4dd3-b1dd-7dc0ffb7ebd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470074301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.3470074301
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1761546948
Short name T161
Test name
Test status
Simulation time 97421968 ps
CPU time 1.24 seconds
Started Mar 14 12:20:01 PM PDT 24
Finished Mar 14 12:20:02 PM PDT 24
Peak memory 199664 kb
Host smart-55bd0e66-b6fe-4a76-9d10-451cf319533d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761546948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1761546948
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3056986023
Short name T96
Test name
Test status
Simulation time 58690810 ps
CPU time 0.66 seconds
Started Mar 14 12:24:23 PM PDT 24
Finished Mar 14 12:24:24 PM PDT 24
Peak memory 199264 kb
Host smart-c8325092-2bf5-45d2-a348-c9591c02b9df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056986023 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3056986023
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.2705591098
Short name T89
Test name
Test status
Simulation time 36605694 ps
CPU time 0.62 seconds
Started Mar 14 12:24:34 PM PDT 24
Finished Mar 14 12:24:35 PM PDT 24
Peak memory 196124 kb
Host smart-c7a97ea1-f6ec-428c-b742-d09419079592
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705591098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2705591098
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2196166742
Short name T78
Test name
Test status
Simulation time 48624138 ps
CPU time 0.75 seconds
Started Mar 14 12:19:08 PM PDT 24
Finished Mar 14 12:19:09 PM PDT 24
Peak memory 197364 kb
Host smart-f31cf55f-de7b-4772-9fab-d411e233ecdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196166742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.2196166742
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.56295968
Short name T15
Test name
Test status
Simulation time 107261634 ps
CPU time 2.25 seconds
Started Mar 14 12:24:34 PM PDT 24
Finished Mar 14 12:24:36 PM PDT 24
Peak memory 200588 kb
Host smart-56e84d84-8db4-42b3-8dd1-daee28f8ee5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56295968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.56295968
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.438356927
Short name T55
Test name
Test status
Simulation time 93293082 ps
CPU time 1.27 seconds
Started Mar 14 12:24:23 PM PDT 24
Finished Mar 14 12:24:25 PM PDT 24
Peak memory 199936 kb
Host smart-78183191-4ed4-405f-9f48-5e14224156cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438356927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.438356927
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2336824163
Short name T130
Test name
Test status
Simulation time 55970097 ps
CPU time 0.97 seconds
Started Mar 14 12:19:02 PM PDT 24
Finished Mar 14 12:19:03 PM PDT 24
Peak memory 200496 kb
Host smart-2c76ae1c-22e0-4bc4-9658-00338e2b0bf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336824163 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2336824163
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.1673693742
Short name T117
Test name
Test status
Simulation time 49475461 ps
CPU time 0.58 seconds
Started Mar 14 12:23:48 PM PDT 24
Finished Mar 14 12:23:49 PM PDT 24
Peak memory 194432 kb
Host smart-256b3d38-a3d2-4d1b-8652-41477e1c3710
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673693742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1673693742
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2227681596
Short name T63
Test name
Test status
Simulation time 12384986 ps
CPU time 0.6 seconds
Started Mar 14 12:19:09 PM PDT 24
Finished Mar 14 12:19:10 PM PDT 24
Peak memory 194112 kb
Host smart-f46895e0-b817-46fa-898c-8f68e0fd1d31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227681596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2227681596
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2243330089
Short name T145
Test name
Test status
Simulation time 83345433 ps
CPU time 0.73 seconds
Started Mar 14 12:23:44 PM PDT 24
Finished Mar 14 12:23:46 PM PDT 24
Peak memory 194284 kb
Host smart-cff766ff-f70a-4c8a-a216-8b16979ad569
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243330089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2243330089
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.2167701632
Short name T39
Test name
Test status
Simulation time 275956603 ps
CPU time 1.21 seconds
Started Mar 14 12:23:51 PM PDT 24
Finished Mar 14 12:23:53 PM PDT 24
Peak memory 200572 kb
Host smart-f698097f-c8fe-4ce0-8abd-55c85f224d00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167701632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2167701632
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3815723264
Short name T5
Test name
Test status
Simulation time 215155851 ps
CPU time 1.44 seconds
Started Mar 14 12:19:08 PM PDT 24
Finished Mar 14 12:19:10 PM PDT 24
Peak memory 200012 kb
Host smart-a36d2d6d-9e9f-4c8f-9d18-6efee604eabb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815723264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3815723264
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1755106807
Short name T43
Test name
Test status
Simulation time 57312135 ps
CPU time 1.03 seconds
Started Mar 14 12:23:48 PM PDT 24
Finished Mar 14 12:23:51 PM PDT 24
Peak memory 200356 kb
Host smart-29470213-928f-4073-b5db-c7466fd3d52a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755106807 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1755106807
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.4005589873
Short name T83
Test name
Test status
Simulation time 60628309 ps
CPU time 0.62 seconds
Started Mar 14 12:23:44 PM PDT 24
Finished Mar 14 12:23:46 PM PDT 24
Peak memory 194332 kb
Host smart-2ac43e55-cd0b-4bfb-b9b0-07fbc708b626
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005589873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.4005589873
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.615998439
Short name T91
Test name
Test status
Simulation time 29256512 ps
CPU time 0.63 seconds
Started Mar 14 12:23:33 PM PDT 24
Finished Mar 14 12:23:34 PM PDT 24
Peak memory 192952 kb
Host smart-55737f2a-2a67-4391-b919-e29ddd91481e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615998439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.615998439
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.133940991
Short name T103
Test name
Test status
Simulation time 41927250 ps
CPU time 0.69 seconds
Started Mar 14 12:23:33 PM PDT 24
Finished Mar 14 12:23:34 PM PDT 24
Peak memory 194120 kb
Host smart-d6ce55a3-110f-4bca-aa00-6f4cd3b1aedf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133940991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr
_outstanding.133940991
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.3888540426
Short name T12
Test name
Test status
Simulation time 123430110 ps
CPU time 1.55 seconds
Started Mar 14 12:24:20 PM PDT 24
Finished Mar 14 12:24:22 PM PDT 24
Peak memory 200060 kb
Host smart-d82d7e6c-fa3f-4500-a532-aa32e71052db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888540426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.3888540426
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3628017600
Short name T60
Test name
Test status
Simulation time 307574492 ps
CPU time 1.31 seconds
Started Mar 14 12:23:44 PM PDT 24
Finished Mar 14 12:23:46 PM PDT 24
Peak memory 197940 kb
Host smart-6dcb976b-85ca-43e5-85f4-42da2c099ce4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628017600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3628017600
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.609810879
Short name T16
Test name
Test status
Simulation time 109813517 ps
CPU time 0.86 seconds
Started Mar 14 12:23:47 PM PDT 24
Finished Mar 14 12:23:49 PM PDT 24
Peak memory 200308 kb
Host smart-aa817fbb-931d-4f82-8da4-729c0a25d38d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609810879 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.609810879
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.2926641323
Short name T113
Test name
Test status
Simulation time 101112455 ps
CPU time 0.56 seconds
Started Mar 14 12:23:45 PM PDT 24
Finished Mar 14 12:23:47 PM PDT 24
Peak memory 194752 kb
Host smart-4fe7c891-21cc-4849-9826-477d8bdd158b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926641323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.2926641323
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2600861387
Short name T156
Test name
Test status
Simulation time 256866175 ps
CPU time 0.68 seconds
Started Mar 14 12:23:47 PM PDT 24
Finished Mar 14 12:23:50 PM PDT 24
Peak memory 195256 kb
Host smart-30cb35d3-539c-4a17-abd5-a415ba42baf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600861387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2600861387
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3486352931
Short name T114
Test name
Test status
Simulation time 17185006 ps
CPU time 0.93 seconds
Started Mar 14 12:23:34 PM PDT 24
Finished Mar 14 12:23:36 PM PDT 24
Peak memory 200188 kb
Host smart-aebafe6c-abb0-40c8-85c9-729e5ae7a58d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486352931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3486352931
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3697967403
Short name T26
Test name
Test status
Simulation time 41735230 ps
CPU time 0.66 seconds
Started Mar 14 12:24:02 PM PDT 24
Finished Mar 14 12:24:03 PM PDT 24
Peak memory 196016 kb
Host smart-5e70219b-2818-447a-8ad7-f88f5ccdfb58
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697967403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3697967403
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1732103289
Short name T155
Test name
Test status
Simulation time 234443568 ps
CPU time 2.11 seconds
Started Mar 14 12:23:40 PM PDT 24
Finished Mar 14 12:23:42 PM PDT 24
Peak memory 198256 kb
Host smart-77065f8c-7b3f-4731-a8a4-3ff7cfc12790
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732103289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1732103289
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.919255579
Short name T48
Test name
Test status
Simulation time 12335271 ps
CPU time 0.64 seconds
Started Mar 14 12:19:44 PM PDT 24
Finished Mar 14 12:19:45 PM PDT 24
Peak memory 196032 kb
Host smart-5cd8d465-b36f-45a8-b31c-d1aa8d1d1926
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919255579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.919255579
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.505895730
Short name T73
Test name
Test status
Simulation time 21947282 ps
CPU time 1 seconds
Started Mar 14 12:22:27 PM PDT 24
Finished Mar 14 12:22:28 PM PDT 24
Peak memory 200384 kb
Host smart-1dfbd25c-ece1-459a-8977-0ea96c1822b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505895730 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.505895730
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.2223279126
Short name T134
Test name
Test status
Simulation time 42106159 ps
CPU time 0.62 seconds
Started Mar 14 12:24:18 PM PDT 24
Finished Mar 14 12:24:19 PM PDT 24
Peak memory 196320 kb
Host smart-dfbf7593-6cc0-47a6-9571-41b1909db0f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223279126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2223279126
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.2223770387
Short name T126
Test name
Test status
Simulation time 15540603 ps
CPU time 0.61 seconds
Started Mar 14 12:23:29 PM PDT 24
Finished Mar 14 12:23:29 PM PDT 24
Peak memory 195084 kb
Host smart-553a1cc1-2f0e-4ca1-9b8f-714b8b38c835
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223770387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2223770387
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2683431713
Short name T148
Test name
Test status
Simulation time 21452315 ps
CPU time 0.66 seconds
Started Mar 14 12:18:54 PM PDT 24
Finished Mar 14 12:18:55 PM PDT 24
Peak memory 196428 kb
Host smart-6fe50ade-0a36-40ec-9979-657551a30e09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683431713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2683431713
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2163160460
Short name T92
Test name
Test status
Simulation time 1232290082 ps
CPU time 1.91 seconds
Started Mar 14 12:21:42 PM PDT 24
Finished Mar 14 12:21:44 PM PDT 24
Peak memory 201024 kb
Host smart-8d8c209b-82f7-406f-bec1-164cb1cf6eda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163160460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2163160460
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3631378959
Short name T44
Test name
Test status
Simulation time 186205327 ps
CPU time 0.94 seconds
Started Mar 14 12:24:18 PM PDT 24
Finished Mar 14 12:24:19 PM PDT 24
Peak memory 199664 kb
Host smart-3ca7e2d9-4b00-4aa7-a733-f334a2b3c2d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631378959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3631378959
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.88761278
Short name T106
Test name
Test status
Simulation time 10945990 ps
CPU time 0.56 seconds
Started Mar 14 12:24:20 PM PDT 24
Finished Mar 14 12:24:21 PM PDT 24
Peak memory 194536 kb
Host smart-740624ff-cce1-4d15-a9b9-e7fe6ba60b28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88761278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.88761278
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2372394354
Short name T8
Test name
Test status
Simulation time 13953864 ps
CPU time 0.63 seconds
Started Mar 14 12:23:47 PM PDT 24
Finished Mar 14 12:23:49 PM PDT 24
Peak memory 192820 kb
Host smart-2b30adda-e41b-4faf-b3b6-b7d6fd44a24e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372394354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2372394354
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1950949306
Short name T152
Test name
Test status
Simulation time 27533074 ps
CPU time 0.64 seconds
Started Mar 14 12:24:28 PM PDT 24
Finished Mar 14 12:24:29 PM PDT 24
Peak memory 194120 kb
Host smart-e88e4f99-6fd2-4e9c-ab97-26a5ea5376b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950949306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1950949306
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.3793508357
Short name T124
Test name
Test status
Simulation time 53142530 ps
CPU time 0.61 seconds
Started Mar 14 12:21:51 PM PDT 24
Finished Mar 14 12:21:51 PM PDT 24
Peak memory 194964 kb
Host smart-ef4b89f0-880b-45d4-8f00-b3149713d937
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793508357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3793508357
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1877588213
Short name T112
Test name
Test status
Simulation time 103249996 ps
CPU time 0.61 seconds
Started Mar 14 12:24:20 PM PDT 24
Finished Mar 14 12:24:21 PM PDT 24
Peak memory 194116 kb
Host smart-d22ca35c-32e7-4c22-af3d-009357dc920c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877588213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1877588213
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.3292470309
Short name T71
Test name
Test status
Simulation time 13640860 ps
CPU time 0.57 seconds
Started Mar 14 12:24:34 PM PDT 24
Finished Mar 14 12:24:35 PM PDT 24
Peak memory 195016 kb
Host smart-74fe4082-79a7-43e2-a169-c46b3f7a31a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292470309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3292470309
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.2409204178
Short name T107
Test name
Test status
Simulation time 59736339 ps
CPU time 0.56 seconds
Started Mar 14 12:24:20 PM PDT 24
Finished Mar 14 12:24:21 PM PDT 24
Peak memory 194404 kb
Host smart-f842f20b-eb75-49e4-9d3e-65dc0d2377f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409204178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.2409204178
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.579695256
Short name T9
Test name
Test status
Simulation time 16887982 ps
CPU time 0.58 seconds
Started Mar 14 12:24:23 PM PDT 24
Finished Mar 14 12:24:24 PM PDT 24
Peak memory 194924 kb
Host smart-a04f7443-21b2-4bc4-9326-be02baa3fcd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579695256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.579695256
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2270188117
Short name T101
Test name
Test status
Simulation time 18208704 ps
CPU time 0.65 seconds
Started Mar 14 12:21:41 PM PDT 24
Finished Mar 14 12:21:42 PM PDT 24
Peak memory 194944 kb
Host smart-6babf9df-92c6-40d4-8a43-6db80d95fcf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270188117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2270188117
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2012243245
Short name T90
Test name
Test status
Simulation time 129509786 ps
CPU time 0.6 seconds
Started Mar 14 12:22:42 PM PDT 24
Finished Mar 14 12:22:43 PM PDT 24
Peak memory 195012 kb
Host smart-ca7f9b18-5948-441c-97e0-b9425ee416ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012243245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2012243245
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.3096230180
Short name T30
Test name
Test status
Simulation time 68563984 ps
CPU time 0.71 seconds
Started Mar 14 12:24:18 PM PDT 24
Finished Mar 14 12:24:19 PM PDT 24
Peak memory 196184 kb
Host smart-3ec0c4c8-cb21-4551-815d-d0dcd5e7174f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096230180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.3096230180
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3232426843
Short name T120
Test name
Test status
Simulation time 155491122 ps
CPU time 1.67 seconds
Started Mar 14 12:19:01 PM PDT 24
Finished Mar 14 12:19:02 PM PDT 24
Peak memory 198700 kb
Host smart-7f575bb4-7d8d-485e-ae1d-196faa916101
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232426843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3232426843
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2709028502
Short name T50
Test name
Test status
Simulation time 19346676 ps
CPU time 0.6 seconds
Started Mar 14 12:23:56 PM PDT 24
Finished Mar 14 12:23:57 PM PDT 24
Peak memory 195952 kb
Host smart-5dfe6bab-f996-4dc3-aaea-a134c18fc185
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709028502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2709028502
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1346465600
Short name T76
Test name
Test status
Simulation time 18550527 ps
CPU time 0.72 seconds
Started Mar 14 12:21:35 PM PDT 24
Finished Mar 14 12:21:36 PM PDT 24
Peak memory 198536 kb
Host smart-d6ae376f-b0f5-495b-aaff-dc1300a905da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346465600 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.1346465600
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.927378709
Short name T160
Test name
Test status
Simulation time 69979649 ps
CPU time 0.63 seconds
Started Mar 14 12:23:39 PM PDT 24
Finished Mar 14 12:23:40 PM PDT 24
Peak memory 194972 kb
Host smart-52797110-1dfc-40d5-9228-33c06d5bdd5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927378709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.927378709
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2178134435
Short name T137
Test name
Test status
Simulation time 134954117 ps
CPU time 0.6 seconds
Started Mar 14 12:21:45 PM PDT 24
Finished Mar 14 12:21:46 PM PDT 24
Peak memory 195092 kb
Host smart-317cadbe-2562-4020-89aa-ed28d5a177cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178134435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2178134435
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2663712898
Short name T98
Test name
Test status
Simulation time 18998851 ps
CPU time 0.76 seconds
Started Mar 14 12:20:01 PM PDT 24
Finished Mar 14 12:20:02 PM PDT 24
Peak memory 197096 kb
Host smart-5fa02748-d06e-4eea-babb-4aed6d8e4442
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663712898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2663712898
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.3599038789
Short name T105
Test name
Test status
Simulation time 49883684 ps
CPU time 1.42 seconds
Started Mar 14 12:19:49 PM PDT 24
Finished Mar 14 12:19:50 PM PDT 24
Peak memory 200652 kb
Host smart-06d5b0ed-6568-4e7a-b372-b59cf9507ed0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599038789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.3599038789
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2148482377
Short name T54
Test name
Test status
Simulation time 176316083 ps
CPU time 1.06 seconds
Started Mar 14 12:22:27 PM PDT 24
Finished Mar 14 12:22:28 PM PDT 24
Peak memory 199660 kb
Host smart-234804ac-9738-438a-b3a6-56df45386490
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148482377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2148482377
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.4150889853
Short name T143
Test name
Test status
Simulation time 42286314 ps
CPU time 0.57 seconds
Started Mar 14 12:21:45 PM PDT 24
Finished Mar 14 12:21:46 PM PDT 24
Peak memory 195016 kb
Host smart-5bae1f60-fe02-43a2-8b99-5eb429749f43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150889853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.4150889853
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3825652974
Short name T108
Test name
Test status
Simulation time 14562444 ps
CPU time 0.58 seconds
Started Mar 14 12:22:42 PM PDT 24
Finished Mar 14 12:22:43 PM PDT 24
Peak memory 195012 kb
Host smart-a933ffea-f167-4f1d-8aed-8b1f10c3f1ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825652974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3825652974
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.1319562571
Short name T61
Test name
Test status
Simulation time 46100061 ps
CPU time 0.57 seconds
Started Mar 14 12:24:01 PM PDT 24
Finished Mar 14 12:24:02 PM PDT 24
Peak memory 194116 kb
Host smart-22cb1397-fc15-422e-85e2-f6f132d46610
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319562571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1319562571
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.334320915
Short name T149
Test name
Test status
Simulation time 14213144 ps
CPU time 0.62 seconds
Started Mar 14 12:24:26 PM PDT 24
Finished Mar 14 12:24:27 PM PDT 24
Peak memory 193908 kb
Host smart-cb5ff8cc-e613-464d-b5d8-20eaf5797bb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334320915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.334320915
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.76086461
Short name T85
Test name
Test status
Simulation time 22390874 ps
CPU time 0.59 seconds
Started Mar 14 12:24:08 PM PDT 24
Finished Mar 14 12:24:09 PM PDT 24
Peak memory 193320 kb
Host smart-f706c4b6-1984-42db-ad21-ab28f753f0be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76086461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.76086461
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.3559349816
Short name T41
Test name
Test status
Simulation time 14006876 ps
CPU time 0.54 seconds
Started Mar 14 12:24:23 PM PDT 24
Finished Mar 14 12:24:24 PM PDT 24
Peak memory 194816 kb
Host smart-dbcbd184-0a5f-4da7-8330-b891f59c2da0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559349816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3559349816
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.3181012549
Short name T65
Test name
Test status
Simulation time 13468039 ps
CPU time 0.61 seconds
Started Mar 14 12:19:13 PM PDT 24
Finished Mar 14 12:19:13 PM PDT 24
Peak memory 195008 kb
Host smart-96409a41-2892-46af-bded-0989a3fdc1ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181012549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3181012549
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1343044418
Short name T95
Test name
Test status
Simulation time 14262841 ps
CPU time 0.58 seconds
Started Mar 14 12:19:09 PM PDT 24
Finished Mar 14 12:19:10 PM PDT 24
Peak memory 193920 kb
Host smart-bcba6afb-7627-41b2-97ef-dc2376f82baf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343044418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1343044418
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.728992687
Short name T29
Test name
Test status
Simulation time 11029876 ps
CPU time 0.62 seconds
Started Mar 14 12:24:08 PM PDT 24
Finished Mar 14 12:24:09 PM PDT 24
Peak memory 193252 kb
Host smart-b8281ac8-2d0c-4627-8004-882502383211
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728992687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.728992687
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.4226154380
Short name T74
Test name
Test status
Simulation time 14197081 ps
CPU time 0.62 seconds
Started Mar 14 12:23:33 PM PDT 24
Finished Mar 14 12:23:34 PM PDT 24
Peak memory 192620 kb
Host smart-53ae711c-06e1-465d-96d9-c3f6d5532629
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226154380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.4226154380
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3083455357
Short name T32
Test name
Test status
Simulation time 50030634 ps
CPU time 0.76 seconds
Started Mar 14 12:19:47 PM PDT 24
Finished Mar 14 12:19:48 PM PDT 24
Peak memory 197116 kb
Host smart-fba31ba8-2915-4697-9b8b-cbe62ff942ec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083455357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3083455357
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3281189562
Short name T80
Test name
Test status
Simulation time 177920350 ps
CPU time 2.62 seconds
Started Mar 14 12:21:42 PM PDT 24
Finished Mar 14 12:21:45 PM PDT 24
Peak memory 198340 kb
Host smart-e9185246-d53d-4020-9910-aec127027ff2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281189562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3281189562
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.1467744238
Short name T147
Test name
Test status
Simulation time 13335819 ps
CPU time 0.59 seconds
Started Mar 14 12:24:02 PM PDT 24
Finished Mar 14 12:24:03 PM PDT 24
Peak memory 195896 kb
Host smart-9f178229-5cff-457f-ac8a-1e653bcdfcb1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467744238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.1467744238
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2287212778
Short name T20
Test name
Test status
Simulation time 70673549 ps
CPU time 0.71 seconds
Started Mar 14 12:22:08 PM PDT 24
Finished Mar 14 12:22:09 PM PDT 24
Peak memory 199052 kb
Host smart-6ab4c0e7-9135-4f74-8e1b-f459819e6676
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287212778 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2287212778
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.3582510662
Short name T81
Test name
Test status
Simulation time 13216311 ps
CPU time 0.57 seconds
Started Mar 14 12:19:10 PM PDT 24
Finished Mar 14 12:19:11 PM PDT 24
Peak memory 196064 kb
Host smart-588d0e88-7b00-443b-b726-99f1cdc430a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582510662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.3582510662
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.3944509122
Short name T6
Test name
Test status
Simulation time 119731264 ps
CPU time 0.6 seconds
Started Mar 14 12:21:20 PM PDT 24
Finished Mar 14 12:21:21 PM PDT 24
Peak memory 195004 kb
Host smart-1a42528e-0f90-4f55-a37f-a520bd1ed6b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944509122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3944509122
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3066971233
Short name T131
Test name
Test status
Simulation time 167486878 ps
CPU time 0.81 seconds
Started Mar 14 12:19:59 PM PDT 24
Finished Mar 14 12:20:00 PM PDT 24
Peak memory 198448 kb
Host smart-ad18e6f5-9425-46bc-b7c8-0210b48a2957
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066971233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.3066971233
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3473975579
Short name T116
Test name
Test status
Simulation time 50509283 ps
CPU time 1.13 seconds
Started Mar 14 12:19:04 PM PDT 24
Finished Mar 14 12:19:06 PM PDT 24
Peak memory 200708 kb
Host smart-55499424-80c7-4305-82f7-9f128b8bd662
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473975579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3473975579
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3004988091
Short name T52
Test name
Test status
Simulation time 54003304 ps
CPU time 0.98 seconds
Started Mar 14 12:21:20 PM PDT 24
Finished Mar 14 12:21:22 PM PDT 24
Peak memory 199176 kb
Host smart-64385e00-8dd1-4619-8358-ce43531af154
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004988091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3004988091
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.1056168924
Short name T99
Test name
Test status
Simulation time 13879334 ps
CPU time 0.56 seconds
Started Mar 14 12:19:22 PM PDT 24
Finished Mar 14 12:19:23 PM PDT 24
Peak memory 195000 kb
Host smart-34213d4b-70e2-4d32-aff5-89c5d7b7293a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056168924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.1056168924
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2566205487
Short name T125
Test name
Test status
Simulation time 13142524 ps
CPU time 0.57 seconds
Started Mar 14 12:19:00 PM PDT 24
Finished Mar 14 12:19:01 PM PDT 24
Peak memory 195040 kb
Host smart-b547afb6-5f71-4ce4-a746-f0ae83a076c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566205487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2566205487
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.126793279
Short name T70
Test name
Test status
Simulation time 16324568 ps
CPU time 0.66 seconds
Started Mar 14 12:21:15 PM PDT 24
Finished Mar 14 12:21:15 PM PDT 24
Peak memory 195112 kb
Host smart-ffe9e65c-7040-47c0-872d-abc03c47fac9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126793279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.126793279
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.2638680565
Short name T10
Test name
Test status
Simulation time 13573956 ps
CPU time 0.62 seconds
Started Mar 14 12:23:47 PM PDT 24
Finished Mar 14 12:23:49 PM PDT 24
Peak memory 192704 kb
Host smart-0b5ba23d-b6af-484f-86bd-40804328fe3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638680565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.2638680565
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3900902224
Short name T72
Test name
Test status
Simulation time 38621295 ps
CPU time 0.56 seconds
Started Mar 14 12:23:36 PM PDT 24
Finished Mar 14 12:23:36 PM PDT 24
Peak memory 194992 kb
Host smart-5836edd0-3a59-4a9b-adb1-9312423e6050
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900902224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3900902224
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2579627255
Short name T153
Test name
Test status
Simulation time 21594845 ps
CPU time 0.64 seconds
Started Mar 14 12:21:14 PM PDT 24
Finished Mar 14 12:21:15 PM PDT 24
Peak memory 195112 kb
Host smart-7a2d87ec-e05f-464b-badc-66f861e0c8e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579627255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2579627255
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2959221182
Short name T49
Test name
Test status
Simulation time 37892621 ps
CPU time 0.58 seconds
Started Mar 14 12:22:12 PM PDT 24
Finished Mar 14 12:22:13 PM PDT 24
Peak memory 195072 kb
Host smart-a20817d4-16b8-45a0-b6cd-52d39983f5c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959221182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2959221182
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.1281038378
Short name T132
Test name
Test status
Simulation time 27316924 ps
CPU time 0.63 seconds
Started Mar 14 12:21:14 PM PDT 24
Finished Mar 14 12:21:15 PM PDT 24
Peak memory 195104 kb
Host smart-1a2c4e5f-84e5-4aee-912a-f5aaffb1ca43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281038378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1281038378
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.1269153943
Short name T151
Test name
Test status
Simulation time 39665186 ps
CPU time 0.59 seconds
Started Mar 14 12:23:33 PM PDT 24
Finished Mar 14 12:23:34 PM PDT 24
Peak memory 192612 kb
Host smart-be839f3b-9c3e-49ef-8be9-b53ce3abf5c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269153943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1269153943
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1362717460
Short name T19
Test name
Test status
Simulation time 21447252 ps
CPU time 0.73 seconds
Started Mar 14 12:19:53 PM PDT 24
Finished Mar 14 12:19:53 PM PDT 24
Peak memory 200392 kb
Host smart-9e076774-27a7-494e-81be-c0b50c2bdf86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362717460 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1362717460
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.608867262
Short name T24
Test name
Test status
Simulation time 12718384 ps
CPU time 0.61 seconds
Started Mar 14 12:24:08 PM PDT 24
Finished Mar 14 12:24:09 PM PDT 24
Peak memory 194812 kb
Host smart-95b9cd13-c0ce-4394-84f3-e204d1845207
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608867262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.608867262
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3801392804
Short name T84
Test name
Test status
Simulation time 110641587 ps
CPU time 0.59 seconds
Started Mar 14 12:19:49 PM PDT 24
Finished Mar 14 12:19:50 PM PDT 24
Peak memory 195004 kb
Host smart-2a286667-d11c-48ae-b26e-1e4a39fdafdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801392804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3801392804
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2123051338
Short name T119
Test name
Test status
Simulation time 24051973 ps
CPU time 0.79 seconds
Started Mar 14 12:21:00 PM PDT 24
Finished Mar 14 12:21:01 PM PDT 24
Peak memory 198408 kb
Host smart-d3113dad-e229-4f17-9521-271bfed160f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123051338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2123051338
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.4099981235
Short name T163
Test name
Test status
Simulation time 120185507 ps
CPU time 1.89 seconds
Started Mar 14 12:19:09 PM PDT 24
Finished Mar 14 12:19:11 PM PDT 24
Peak memory 199592 kb
Host smart-7a58551d-ff42-416f-8df2-b1c1c61f53e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099981235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.4099981235
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.351567142
Short name T142
Test name
Test status
Simulation time 42103209 ps
CPU time 0.96 seconds
Started Mar 14 12:19:59 PM PDT 24
Finished Mar 14 12:20:00 PM PDT 24
Peak memory 199328 kb
Host smart-92d47501-65d7-41e1-9f29-fdb30f04b352
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351567142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.351567142
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1145193195
Short name T102
Test name
Test status
Simulation time 22150554 ps
CPU time 1.06 seconds
Started Mar 14 12:19:45 PM PDT 24
Finished Mar 14 12:19:47 PM PDT 24
Peak memory 200516 kb
Host smart-03eeb0ec-30cc-48a1-93fe-797ddd23da01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145193195 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1145193195
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.2242141743
Short name T79
Test name
Test status
Simulation time 28376252 ps
CPU time 0.59 seconds
Started Mar 14 12:24:24 PM PDT 24
Finished Mar 14 12:24:25 PM PDT 24
Peak memory 195792 kb
Host smart-11ee5cc7-966a-479d-841f-37d21d06b540
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242141743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2242141743
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.4243836555
Short name T111
Test name
Test status
Simulation time 33194616 ps
CPU time 0.55 seconds
Started Mar 14 12:19:22 PM PDT 24
Finished Mar 14 12:19:23 PM PDT 24
Peak memory 195004 kb
Host smart-4cce72e3-6a43-4053-a63b-48559e4b63a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243836555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.4243836555
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.2637354035
Short name T23
Test name
Test status
Simulation time 101733139 ps
CPU time 0.65 seconds
Started Mar 14 12:19:41 PM PDT 24
Finished Mar 14 12:19:42 PM PDT 24
Peak memory 195012 kb
Host smart-7b9a078f-e488-4b22-902c-e36fb84bd137
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637354035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.2637354035
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1754627860
Short name T40
Test name
Test status
Simulation time 73357167 ps
CPU time 1.64 seconds
Started Mar 14 12:23:45 PM PDT 24
Finished Mar 14 12:23:48 PM PDT 24
Peak memory 200244 kb
Host smart-6b6073eb-f178-4bf8-9baf-3bb71d1b6138
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754627860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1754627860
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.1928143055
Short name T53
Test name
Test status
Simulation time 387816844 ps
CPU time 1.3 seconds
Started Mar 14 12:20:19 PM PDT 24
Finished Mar 14 12:20:20 PM PDT 24
Peak memory 199892 kb
Host smart-9320f0b5-077d-4ec2-aff5-cd82eb477757
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928143055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.1928143055
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.229147858
Short name T17
Test name
Test status
Simulation time 37604171 ps
CPU time 0.65 seconds
Started Mar 14 12:19:59 PM PDT 24
Finished Mar 14 12:19:59 PM PDT 24
Peak memory 198676 kb
Host smart-966fe2d5-5eec-4382-98bc-ceccbc47d910
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229147858 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.229147858
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.3721165930
Short name T136
Test name
Test status
Simulation time 42696114 ps
CPU time 0.62 seconds
Started Mar 14 12:20:12 PM PDT 24
Finished Mar 14 12:20:13 PM PDT 24
Peak memory 196048 kb
Host smart-cfd818ff-95e4-47f2-b43b-d95126208d8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721165930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3721165930
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.4029685214
Short name T75
Test name
Test status
Simulation time 106421877 ps
CPU time 0.65 seconds
Started Mar 14 12:21:12 PM PDT 24
Finished Mar 14 12:21:13 PM PDT 24
Peak memory 194960 kb
Host smart-90c91c77-b9b8-4383-9634-fd761217b25c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029685214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.4029685214
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.1985426401
Short name T22
Test name
Test status
Simulation time 19258311 ps
CPU time 0.72 seconds
Started Mar 14 12:20:25 PM PDT 24
Finished Mar 14 12:20:26 PM PDT 24
Peak memory 196492 kb
Host smart-61634a89-f40a-4ba1-be49-8f08b282d5b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985426401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.1985426401
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2015649176
Short name T162
Test name
Test status
Simulation time 109482743 ps
CPU time 2.39 seconds
Started Mar 14 12:20:18 PM PDT 24
Finished Mar 14 12:20:20 PM PDT 24
Peak memory 200628 kb
Host smart-7aea5a38-8b70-4268-9454-04ae8ed66d0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015649176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2015649176
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.1740723619
Short name T68
Test name
Test status
Simulation time 59960577 ps
CPU time 0.71 seconds
Started Mar 14 12:22:07 PM PDT 24
Finished Mar 14 12:22:08 PM PDT 24
Peak memory 198732 kb
Host smart-a46641f6-82d9-4ff4-8070-6b9613707724
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740723619 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.1740723619
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3455515881
Short name T139
Test name
Test status
Simulation time 45137127 ps
CPU time 0.6 seconds
Started Mar 14 12:19:59 PM PDT 24
Finished Mar 14 12:20:00 PM PDT 24
Peak memory 196220 kb
Host smart-069c6a12-c83f-41ff-bcbf-4c03d90e5286
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455515881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3455515881
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.1836165667
Short name T36
Test name
Test status
Simulation time 52297065 ps
CPU time 0.57 seconds
Started Mar 14 12:20:29 PM PDT 24
Finished Mar 14 12:20:30 PM PDT 24
Peak memory 194976 kb
Host smart-33d37c18-6507-42b6-9d16-e1b386713872
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836165667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1836165667
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.4245008268
Short name T45
Test name
Test status
Simulation time 23261476 ps
CPU time 0.66 seconds
Started Mar 14 12:21:20 PM PDT 24
Finished Mar 14 12:21:22 PM PDT 24
Peak memory 196260 kb
Host smart-be110cda-9def-4d44-a3c3-8dc7d15c5f8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245008268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.4245008268
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2129237684
Short name T110
Test name
Test status
Simulation time 19116916 ps
CPU time 0.93 seconds
Started Mar 14 12:24:02 PM PDT 24
Finished Mar 14 12:24:03 PM PDT 24
Peak memory 200272 kb
Host smart-be0d64f3-de0d-45a2-b29d-207485655ce3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129237684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2129237684
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.4221308964
Short name T118
Test name
Test status
Simulation time 42597885 ps
CPU time 1.06 seconds
Started Mar 14 12:20:12 PM PDT 24
Finished Mar 14 12:20:13 PM PDT 24
Peak memory 199468 kb
Host smart-a5632795-d95c-40e9-b44e-4d2b275907fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221308964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.4221308964
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.3749009420
Short name T86
Test name
Test status
Simulation time 32055703 ps
CPU time 0.86 seconds
Started Mar 14 12:20:20 PM PDT 24
Finished Mar 14 12:20:21 PM PDT 24
Peak memory 200456 kb
Host smart-4c758503-dd0c-4d80-a58b-62e12b083921
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749009420 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.3749009420
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.555705768
Short name T33
Test name
Test status
Simulation time 40217346 ps
CPU time 0.59 seconds
Started Mar 14 12:24:24 PM PDT 24
Finished Mar 14 12:24:25 PM PDT 24
Peak memory 196228 kb
Host smart-76f1ef92-548d-450e-a753-b34a1f5c2f63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555705768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.555705768
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.717530258
Short name T146
Test name
Test status
Simulation time 13258084 ps
CPU time 0.56 seconds
Started Mar 14 12:24:15 PM PDT 24
Finished Mar 14 12:24:15 PM PDT 24
Peak memory 194920 kb
Host smart-9b3818ef-229a-46a9-aa48-c4779c67ce88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717530258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.717530258
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.882259070
Short name T3
Test name
Test status
Simulation time 24268780 ps
CPU time 0.68 seconds
Started Mar 14 12:20:39 PM PDT 24
Finished Mar 14 12:20:40 PM PDT 24
Peak memory 198492 kb
Host smart-bbabbf05-fcb7-47b2-9d57-1602f433d51e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882259070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr_
outstanding.882259070
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.3140890897
Short name T21
Test name
Test status
Simulation time 211126018 ps
CPU time 1.96 seconds
Started Mar 14 12:21:42 PM PDT 24
Finished Mar 14 12:21:44 PM PDT 24
Peak memory 200600 kb
Host smart-2bfdca44-3dd8-446b-b6af-1b28d41facb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140890897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3140890897
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.373149468
Short name T57
Test name
Test status
Simulation time 162893367 ps
CPU time 1.44 seconds
Started Mar 14 12:21:22 PM PDT 24
Finished Mar 14 12:21:23 PM PDT 24
Peak memory 200204 kb
Host smart-be687d9d-32d2-40f2-baf7-8e0ac2ef2717
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373149468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.373149468
Directory /workspace/9.uart_tl_intg_err/latest
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