Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_break_err_cg

Group : uart_env_pkg::uart_env_cov::rx_break_err_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
25.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_break_err_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	4	3	1	25.00

Variables for Group uart_env_pkg::uart_env_cov::rx_break_err_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_break_level	4	3	1	25.00	100	1	1	0

Summary for Variable cp_break_level

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	3	1	25.00

User Defined Bins for cp_break_level

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
all_levels[1]	0	1	1
all_levels[2]	0	1	1
all_levels[3]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_levels[0]

125

1

T2

7

T6

3

T8

3