Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	131	131	0	0.00
Crosses	258	258	0	0.00

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	129	129	0	0.00	100	1	1	0
cp_rst	2	2	0	0.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	258	258	0	0.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	129	0	0.00

User Defined Bins for cp_lvl

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
all_levels[0]	0	1	1
all_levels[1]	0	1	1
all_levels[2]	0	1	1
all_levels[3]	0	1	1
all_levels[4]	0	1	1
all_levels[5]	0	1	1
all_levels[6]	0	1	1
all_levels[7]	0	1	1
all_levels[8]	0	1	1
all_levels[9]	0	1	1
all_levels[10]	0	1	1
all_levels[11]	0	1	1
all_levels[12]	0	1	1
all_levels[13]	0	1	1
all_levels[14]	0	1	1
all_levels[15]	0	1	1
all_levels[16]	0	1	1
all_levels[17]	0	1	1
all_levels[18]	0	1	1
all_levels[19]	0	1	1
all_levels[20]	0	1	1
all_levels[21]	0	1	1
all_levels[22]	0	1	1
all_levels[23]	0	1	1
all_levels[24]	0	1	1
all_levels[25]	0	1	1
all_levels[26]	0	1	1
all_levels[27]	0	1	1
all_levels[28]	0	1	1
all_levels[29]	0	1	1
all_levels[30]	0	1	1
all_levels[31]	0	1	1
all_levels[32]	0	1	1
all_levels[33]	0	1	1
all_levels[34]	0	1	1
all_levels[35]	0	1	1
all_levels[36]	0	1	1
all_levels[37]	0	1	1
all_levels[38]	0	1	1
all_levels[39]	0	1	1
all_levels[40]	0	1	1
all_levels[41]	0	1	1
all_levels[42]	0	1	1
all_levels[43]	0	1	1
all_levels[44]	0	1	1
all_levels[45]	0	1	1
all_levels[46]	0	1	1
all_levels[47]	0	1	1
all_levels[48]	0	1	1
all_levels[49]	0	1	1
all_levels[50]	0	1	1
all_levels[51]	0	1	1
all_levels[52]	0	1	1
all_levels[53]	0	1	1
all_levels[54]	0	1	1
all_levels[55]	0	1	1
all_levels[56]	0	1	1
all_levels[57]	0	1	1
all_levels[58]	0	1	1
all_levels[59]	0	1	1
all_levels[60]	0	1	1
all_levels[61]	0	1	1
all_levels[62]	0	1	1
all_levels[63]	0	1	1
all_levels[64]	0	1	1
all_levels[65]	0	1	1
all_levels[66]	0	1	1
all_levels[67]	0	1	1
all_levels[68]	0	1	1
all_levels[69]	0	1	1
all_levels[70]	0	1	1
all_levels[71]	0	1	1
all_levels[72]	0	1	1
all_levels[73]	0	1	1
all_levels[74]	0	1	1
all_levels[75]	0	1	1
all_levels[76]	0	1	1
all_levels[77]	0	1	1
all_levels[78]	0	1	1
all_levels[79]	0	1	1
all_levels[80]	0	1	1
all_levels[81]	0	1	1
all_levels[82]	0	1	1
all_levels[83]	0	1	1
all_levels[84]	0	1	1
all_levels[85]	0	1	1
all_levels[86]	0	1	1
all_levels[87]	0	1	1
all_levels[88]	0	1	1
all_levels[89]	0	1	1
all_levels[90]	0	1	1
all_levels[91]	0	1	1
all_levels[92]	0	1	1
all_levels[93]	0	1	1
all_levels[94]	0	1	1
all_levels[95]	0	1	1
all_levels[96]	0	1	1
all_levels[97]	0	1	1
all_levels[98]	0	1	1
all_levels[99]	0	1	1
all_levels[100]	0	1	1
all_levels[101]	0	1	1
all_levels[102]	0	1	1
all_levels[103]	0	1	1
all_levels[104]	0	1	1
all_levels[105]	0	1	1
all_levels[106]	0	1	1
all_levels[107]	0	1	1
all_levels[108]	0	1	1
all_levels[109]	0	1	1
all_levels[110]	0	1	1
all_levels[111]	0	1	1
all_levels[112]	0	1	1
all_levels[113]	0	1	1
all_levels[114]	0	1	1
all_levels[115]	0	1	1
all_levels[116]	0	1	1
all_levels[117]	0	1	1
all_levels[118]	0	1	1
all_levels[119]	0	1	1
all_levels[120]	0	1	1
all_levels[121]	0	1	1
all_levels[122]	0	1	1
all_levels[123]	0	1	1
all_levels[124]	0	1	1
all_levels[125]	0	1	1
all_levels[126]	0	1	1
all_levels[127]	0	1	1
all_levels[128]	0	1	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_rst

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	258	258	0	0.00	258

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	258