Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	344	1			T2	8		T6	5		T12	1
all_pins[1]	344	1			T2	8		T6	5		T12	1
all_pins[2]	344	1			T2	8		T6	5		T12	1
all_pins[3]	344	1			T2	8		T6	5		T12	1
all_pins[4]	344	1			T2	8		T6	5		T12	1
all_pins[5]	344	1			T2	8		T6	5		T12	1
all_pins[6]	344	1			T2	8		T6	5		T12	1
all_pins[7]	344	1			T2	8		T6	5		T12	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2206	1			T2	46		T6	29		T12	8
values[0x1]	546	1			T2	18		T6	11		T8	13
transitions[0x0=>0x1]	393	1			T2	12		T6	7		T8	7
transitions[0x1=>0x0]	379	1			T2	12		T6	7		T8	6

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	191	1			T2	4		T6	5		T12	1
all_pins[0]	values[0x1]	153	1			T2	4		T8	4		T29	4
all_pins[0]	transitions[0x0=>0x1]	125	1			T2	3		T8	2		T29	3
all_pins[0]	transitions[0x1=>0x0]	30	1			T2	1		T6	1		T9	1
all_pins[1]	values[0x0]	286	1			T2	6		T6	4		T12	1
all_pins[1]	values[0x1]	58	1			T2	2		T6	1		T8	2
all_pins[1]	transitions[0x0=>0x1]	45	1			T2	1		T6	1		T8	2
all_pins[1]	transitions[0x1=>0x0]	38	1			T2	2		T6	1		T9	1
all_pins[2]	values[0x0]	293	1			T2	5		T6	4		T12	1
all_pins[2]	values[0x1]	51	1			T2	3		T6	1		T9	2
all_pins[2]	transitions[0x0=>0x1]	37	1			T2	2		T6	1		T9	1
all_pins[2]	transitions[0x1=>0x0]	45	1			T2	3		T6	1		T29	2
all_pins[3]	values[0x0]	285	1			T2	4		T6	4		T12	1
all_pins[3]	values[0x1]	59	1			T2	4		T6	1		T29	2
all_pins[3]	transitions[0x0=>0x1]	42	1			T2	4		T9	1		T36	3
all_pins[3]	transitions[0x1=>0x0]	38	1			T2	1		T6	2		T8	3
all_pins[4]	values[0x0]	289	1			T2	7		T6	2		T12	1
all_pins[4]	values[0x1]	55	1			T2	1		T6	3		T8	3
all_pins[4]	transitions[0x0=>0x1]	38	1			T8	1		T29	2		T10	2
all_pins[4]	transitions[0x1=>0x0]	39	1			T2	1		T29	1		T9	1
all_pins[5]	values[0x0]	288	1			T2	6		T6	2		T12	1
all_pins[5]	values[0x1]	56	1			T2	2		T6	3		T8	2
all_pins[5]	transitions[0x0=>0x1]	36	1			T2	1		T6	3		T8	2
all_pins[5]	transitions[0x1=>0x0]	39	1			T10	3		T36	1		T38	2
all_pins[6]	values[0x0]	285	1			T2	7		T6	5		T12	1
all_pins[6]	values[0x1]	59	1			T2	1		T10	3		T61	2
all_pins[6]	transitions[0x0=>0x1]	47	1			T2	1		T10	3		T61	2
all_pins[6]	transitions[0x1=>0x0]	43	1			T2	1		T6	2		T8	2
all_pins[7]	values[0x0]	289	1			T2	7		T6	3		T12	1
all_pins[7]	values[0x1]	55	1			T2	1		T6	2		T8	2
all_pins[7]	transitions[0x0=>0x1]	23	1			T6	2		T9	1		T38	2
all_pins[7]	transitions[0x1=>0x0]	107	1			T2	3		T8	1		T29	3