Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
0.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	35	0	0.00
Crosses	66	66	0	0.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	33	0	0.00	100	1	1	0
cp_rst	2	2	0	0.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	66	0	0.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	33	0	0.00

User Defined Bins for cp_lvl

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
all_levels[0]	0	1	1
all_levels[1]	0	1	1
all_levels[2]	0	1	1
all_levels[3]	0	1	1
all_levels[4]	0	1	1
all_levels[5]	0	1	1
all_levels[6]	0	1	1
all_levels[7]	0	1	1
all_levels[8]	0	1	1
all_levels[9]	0	1	1
all_levels[10]	0	1	1
all_levels[11]	0	1	1
all_levels[12]	0	1	1
all_levels[13]	0	1	1
all_levels[14]	0	1	1
all_levels[15]	0	1	1
all_levels[16]	0	1	1
all_levels[17]	0	1	1
all_levels[18]	0	1	1
all_levels[19]	0	1	1
all_levels[20]	0	1	1
all_levels[21]	0	1	1
all_levels[22]	0	1	1
all_levels[23]	0	1	1
all_levels[24]	0	1	1
all_levels[25]	0	1	1
all_levels[26]	0	1	1
all_levels[27]	0	1	1
all_levels[28]	0	1	1
all_levels[29]	0	1	1
all_levels[30]	0	1	1
all_levels[31]	0	1	1
all_levels[32]	0	1	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	2	0	0.00

Automatically Generated Bins for cp_rst

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	--	--	2

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	66	0	0.00	66

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	66