Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.55	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	4	44	91.67

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	4	44	91.67	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1			T2	7		T6	4		T8	4
all_values[1]	275	1			T2	7		T6	4		T8	4
all_values[2]	275	1			T2	7		T6	4		T8	4
all_values[3]	275	1			T2	7		T6	4		T8	4
all_values[4]	275	1			T2	7		T6	4		T8	4
all_values[5]	275	1			T2	7		T6	4		T8	4
all_values[6]	275	1			T2	7		T6	4		T8	4
all_values[7]	275	1			T2	7		T6	4		T8	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1269

1

T2

34

T6

20

T8

17

auto[1]

931

1

T2

22

T6

12

T8

15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

838

1

T2

15

T6

8

T8

12

auto[1]

1362

1

T2

41

T6

24

T8

20

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1334

1

T2

29

T6

17

T8

19

auto[1]

866

1

T2

27

T6

15

T8

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	4	44	91.67	4
Automatically Generated Cross Bins	48	4	44	91.67	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	98	1			T2	2		T6	3		T29	1
all_values[0]	auto[0]	auto[1]	auto[1]	74	1			T2	2		T8	1		T29	3
all_values[0]	auto[1]	auto[0]	auto[1]	60	1			T2	2		T6	1		T8	2
all_values[0]	auto[1]	auto[1]	auto[1]	43	1			T2	1		T8	1		T10	3
all_values[1]	auto[0]	auto[0]	auto[0]	85	1			T2	2		T6	1		T8	1
all_values[1]	auto[0]	auto[1]	auto[0]	78	1			T6	2		T8	1		T29	3
all_values[1]	auto[1]	auto[0]	auto[1]	63	1			T2	3		T10	2		T9	2
all_values[1]	auto[1]	auto[1]	auto[1]	49	1			T2	2		T6	1		T8	2
all_values[2]	auto[0]	auto[0]	auto[0]	59	1			T8	3		T29	1		T10	2
all_values[2]	auto[0]	auto[0]	auto[1]	34	1			T6	1		T10	2		T61	1
all_values[2]	auto[0]	auto[1]	auto[0]	46	1			T2	2		T29	1		T9	1
all_values[2]	auto[0]	auto[1]	auto[1]	25	1			T2	1		T61	2		T62	1
all_values[2]	auto[1]	auto[0]	auto[1]	66	1			T2	1		T6	3		T8	1
all_values[2]	auto[1]	auto[1]	auto[1]	45	1			T2	3		T9	3		T61	1
all_values[3]	auto[0]	auto[0]	auto[0]	86	1			T2	2		T6	2		T8	1
all_values[3]	auto[0]	auto[0]	auto[1]	24	1			T2	1		T10	2		T9	4
all_values[3]	auto[0]	auto[1]	auto[0]	37	1			T8	2		T29	1		T62	1
all_values[3]	auto[0]	auto[1]	auto[1]	23	1			T2	2		T29	1		T9	1
all_values[3]	auto[1]	auto[0]	auto[1]	57	1			T2	1		T6	1		T29	2
all_values[3]	auto[1]	auto[1]	auto[1]	48	1			T2	1		T6	1		T8	1
all_values[4]	auto[0]	auto[0]	auto[0]	59	1			T2	2		T29	1		T10	1
all_values[4]	auto[0]	auto[0]	auto[1]	30	1			T2	1		T41	1		T63	1
all_values[4]	auto[0]	auto[1]	auto[0]	45	1			T10	2		T9	1		T61	2
all_values[4]	auto[0]	auto[1]	auto[1]	29	1			T6	1		T8	2		T29	1
all_values[4]	auto[1]	auto[0]	auto[1]	64	1			T2	2		T6	1		T8	2
all_values[4]	auto[1]	auto[1]	auto[1]	48	1			T2	2		T6	2		T10	2
all_values[5]	auto[0]	auto[0]	auto[0]	71	1			T6	1		T29	1		T10	5
all_values[5]	auto[0]	auto[0]	auto[1]	32	1			T2	2		T8	1		T10	1
all_values[5]	auto[0]	auto[1]	auto[0]	42	1			T9	1		T36	1		T38	1
all_values[5]	auto[0]	auto[1]	auto[1]	23	1			T6	1		T8	1		T29	1
all_values[5]	auto[1]	auto[0]	auto[1]	65	1			T2	4		T8	1		T29	1
all_values[5]	auto[1]	auto[1]	auto[1]	42	1			T2	1		T6	2		T8	1
all_values[6]	auto[0]	auto[0]	auto[0]	74	1			T2	3		T8	2		T29	2
all_values[6]	auto[0]	auto[0]	auto[1]	23	1			T2	1		T6	2		T8	1
all_values[6]	auto[0]	auto[1]	auto[0]	41	1			T2	1		T9	3		T61	2
all_values[6]	auto[0]	auto[1]	auto[1]	27	1			T10	2		T61	1		T38	1
all_values[6]	auto[1]	auto[0]	auto[1]	67	1			T2	1		T6	2		T8	1
all_values[6]	auto[1]	auto[1]	auto[1]	43	1			T2	1		T10	1		T9	1
all_values[7]	auto[0]	auto[0]	auto[0]	60	1			T2	2		T6	2		T8	1
all_values[7]	auto[0]	auto[0]	auto[1]	36	1			T2	1		T10	1		T9	1
all_values[7]	auto[0]	auto[1]	auto[0]	55	1			T2	1		T8	1		T29	1
all_values[7]	auto[0]	auto[1]	auto[1]	18	1			T2	1		T6	1		T8	1
all_values[7]	auto[1]	auto[0]	auto[1]	56	1			T2	1		T29	2		T10	1
all_values[7]	auto[1]	auto[1]	auto[1]	50	1			T2	1		T6	1		T8	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal