Line Coverage for Module :
prim_subreg
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Module :
prim_subreg ( parameter DW=24,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_subreg ( parameter DW=2,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_subreg ( parameter DW=16,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_subreg ( parameter DW=8,SwAccess=2,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
Cond Coverage for Module :
prim_subreg ( parameter DW=3,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_subreg ( parameter DW=1,SwAccess=1,RESVAL,Mubi=0 + DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL=0,Mubi=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_subreg
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_tx_watermark
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 6 | 85.71 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
64 |
1 |
1 |
65 |
0 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_tx_watermark
| Total | Covered | Percent |
Conditions | 2 | 1 | 50.00 |
Logical | 2 | 1 | 50.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_state_tx_watermark
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
3 |
60.00 |
TERNARY |
64 |
2 |
1 |
50.00 |
IF |
56 |
3 |
2 |
66.67 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_watermark
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 6 | 85.71 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
64 |
1 |
1 |
65 |
0 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_watermark
| Total | Covered | Percent |
Conditions | 2 | 1 | 50.00 |
Logical | 2 | 1 | 50.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_watermark
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
3 |
60.00 |
TERNARY |
64 |
2 |
1 |
50.00 |
IF |
56 |
3 |
2 |
66.67 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_tx_empty
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 6 | 85.71 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 0 | 0.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
==> MISSING_ELSE |
64 |
1 |
1 |
65 |
0 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_tx_empty
| Total | Covered | Percent |
Conditions | 2 | 1 | 50.00 |
Logical | 2 | 1 | 50.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_state_tx_empty
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
3 |
60.00 |
TERNARY |
64 |
2 |
1 |
50.00 |
IF |
56 |
3 |
2 |
66.67 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_tx_done
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_tx_done
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_state_tx_done
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_overflow
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_overflow
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_overflow
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_frame_err
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_frame_err
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_frame_err
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_break_err
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_break_err
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_break_err
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_timeout
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_timeout
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_timeout
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_parity_err
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_parity_err
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_state_rx_parity_err
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_tx_watermark
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_tx_watermark
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_tx_watermark
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_watermark
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_watermark
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_watermark
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_tx_done
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_tx_done
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_tx_done
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_overflow
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_overflow
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_overflow
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_frame_err
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_frame_err
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_frame_err
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_break_err
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_break_err
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_break_err
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_timeout
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_timeout
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_timeout
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_parity_err
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_parity_err
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_rx_parity_err
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_tx_empty
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_tx_empty
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_tx_empty
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_ctrl_tx
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ctrl_tx
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ctrl_tx
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_ctrl_rx
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ctrl_rx
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ctrl_rx
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_ctrl_nf
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ctrl_nf
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ctrl_nf
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_ctrl_slpbk
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ctrl_slpbk
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ctrl_slpbk
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_ctrl_llpbk
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ctrl_llpbk
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ctrl_llpbk
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_ctrl_parity_en
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ctrl_parity_en
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ctrl_parity_en
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_ctrl_parity_odd
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ctrl_parity_odd
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ctrl_parity_odd
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_ctrl_rxblvl
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ctrl_rxblvl
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ctrl_rxblvl
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_ctrl_nco
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ctrl_nco
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_ctrl_nco
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_wdata
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_wdata
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.u_reg.u_wdata
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T4 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_fifo_ctrl_rxrst
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_fifo_ctrl_rxrst
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_fifo_ctrl_rxrst
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_fifo_ctrl_txrst
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_fifo_ctrl_txrst
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_fifo_ctrl_txrst
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_fifo_ctrl_rxilvl
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_fifo_ctrl_rxilvl
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_fifo_ctrl_rxilvl
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_fifo_ctrl_txilvl
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_fifo_ctrl_txilvl
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_fifo_ctrl_txilvl
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_ovrd_txen
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ovrd_txen
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T15,T13 |
Branch Coverage for Instance : tb.dut.u_reg.u_ovrd_txen
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T15,T13 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T15,T13 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_ovrd_txval
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_ovrd_txval
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T5,T15,T13 |
Branch Coverage for Instance : tb.dut.u_reg.u_ovrd_txval
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T5,T15,T13 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T5,T15,T13 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_timeout_ctrl_val
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_timeout_ctrl_val
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_timeout_ctrl_val
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_timeout_ctrl_en
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_timeout_ctrl_en
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_timeout_ctrl_en
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |