UART Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	32.060s	6.265ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.890s	1.030ms	5	5	100.00
V1	csr_rw	uart_csr_rw	0.720s	17.852us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.580s	273.221us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	0.850s	29.859us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.520s	31.168us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.720s	17.852us	20	20	100.00
		uart_csr_aliasing	0.850s	29.859us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.132m	94.123ms	50	50	100.00
V2	parity	uart_smoke	32.060s	6.265ms	50	50	100.00
		uart_tx_rx	3.132m	94.123ms	50	50	100.00
V2	parity_error	uart_intr	7.789m	353.061ms	50	50	100.00
		uart_rx_parity_err	4.909m	195.900ms	50	50	100.00
V2	watermark	uart_tx_rx	3.132m	94.123ms	50	50	100.00
		uart_intr	7.789m	353.061ms	50	50	100.00
V2	fifo_full	uart_fifo_full	10.649m	224.452ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	3.956m	154.212ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	9.278m	47.530ms	300	300	100.00
V2	rx_frame_err	uart_intr	7.789m	353.061ms	50	50	100.00
V2	rx_break_err	uart_intr	7.789m	353.061ms	50	50	100.00
V2	rx_timeout	uart_intr	7.789m	353.061ms	50	50	100.00
V2	perf	uart_perf	23.530m	31.294ms	50	50	100.00
V2	sys_loopback	uart_loopback	24.680s	9.070ms	50	50	100.00
V2	line_loopback	uart_loopback	24.680s	9.070ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	1.509m	134.108ms	10	50	20.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.118m	82.525ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	26.930s	7.034ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.150m	7.086ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	21.041m	173.291ms	49	50	98.00
V2	stress_all	uart_stress_all	34.432m	117.813ms	36	50	72.00
V2	alert_test	uart_alert_test	0.640s	13.702us	50	50	100.00
V2	intr_test	uart_intr_test	0.650s	15.020us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.530s	182.852us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.530s	182.852us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.890s	1.030ms	5	5	100.00
		uart_csr_rw	0.720s	17.852us	20	20	100.00
		uart_csr_aliasing	0.850s	29.859us	5	5	100.00
		uart_same_csr_outstanding	0.810s	59.660us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.890s	1.030ms	5	5	100.00
		uart_csr_rw	0.720s	17.852us	20	20	100.00
		uart_csr_aliasing	0.850s	29.859us	5	5	100.00
		uart_same_csr_outstanding	0.810s	59.660us	20	20	100.00
V2		TOTAL			1035	1090	94.95
V2S	tl_intg_err	uart_sec_cm	0.890s	395.118us	5	5	100.00
		uart_tl_intg_err	1.460s	358.042us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.460s	358.042us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	25.272m	369.665ms	67	100	67.00
V3		TOTAL			67	100	67.00
		TOTAL			1232	1320	93.33

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	18	18	15	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.10	99.10	97.65	100.00	--	98.38	100.00	99.50

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:390) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 46 failures:

Test uart_stress_all_with_rand_reset has 21 failures.

0.uart_stress_all_with_rand_reset.71700585895426028132648817912728937153946568845608170027947841387347971408450
Line 440, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 40166788324 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 40166788324 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_INFO @ 40474308324 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 14/125
  UVM_ERROR @ 40475908324 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
  UVM_ERROR @ 40476188324 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty

9.uart_stress_all_with_rand_reset.52609870590266716270577990278317988720252791359739823127272966250380979413801
Line 337, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/9.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 20488175005 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 20701385044 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 20701385044 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_INFO @ 20731426951 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/735
  UVM_ERROR @ 20858886304 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1

... and 19 more failures.

Test uart_noise_filter has 17 failures.

1.uart_noise_filter.55263451375532986150441352009069550089694690696274379696217377662397644105932
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/1.uart_noise_filter/latest/run.log

  UVM_ERROR @   9899636 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @  13253749 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @  14128735 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @  96794079 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0
  UVM_ERROR @  96814912 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty

2.uart_noise_filter.82241777313363388965061318773649971979657529113694131783330188854853826429274
Line 252, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/2.uart_noise_filter/latest/run.log

  UVM_ERROR @ 10365617360 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 10365617360 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 10630267360 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 2,                                 clk_pulses: 0
  UVM_ERROR @ 10630297360 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 10630307360 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (5 [0x5] vs 127 [0x7f]) reg name: uart_reg_block.rdata

... and 15 more failures.

Test uart_stress_all has 8 failures.

19.uart_stress_all.49149156350623856312611836659216339518658454932336196312679726832520101122642
Line 328, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/19.uart_stress_all/latest/run.log

  UVM_ERROR @ 219582033926 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 219587242301 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 219633409337 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 219634659347 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 219637242701 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0

25.uart_stress_all.8705122219336101859144266466598310253021159372338344667474241637421287543200
Line 271, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/25.uart_stress_all/latest/run.log

  UVM_ERROR @ 9204224503 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 9204780063 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 9205335623 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 9205891183 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 9206446743 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

... and 6 more failures.

UVM_ERROR (uart_scoreboard.sv:498) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 23 failures:

Test uart_stress_all has 3 failures.

3.uart_stress_all.88274357236320861945363239783354804416372500768564592619209330918428968330529
Line 333, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/3.uart_stress_all/latest/run.log

  UVM_ERROR @ 72699879591 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
  UVM_ERROR @ 72699921258 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 72699962925 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (30 [0x1e] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 72713629701 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 72713629701 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

5.uart_stress_all.96172579313882610454633349776335462688947444251546795343162352007641263610557
Line 255, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/5.uart_stress_all/latest/run.log

  UVM_ERROR @ 9409669307 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
  UVM_ERROR @ 9409679511 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 9409740735 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (240 [0xf0] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 9672412103 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 9672412103 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

... and 1 more failures.

Test uart_noise_filter has 14 failures.

6.uart_noise_filter.68910042318437376739037539855260972200239350636636732264496739633022607778513
Line 251, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/6.uart_noise_filter/latest/run.log

  UVM_ERROR @ 10123907472 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0
  UVM_ERROR @ 10123927880 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 10123948288 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (230 [0xe6] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 10123968696 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 10123989104 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (230 [0xe6] vs 251 [0xfb]) reg name: uart_reg_block.rdata

8.uart_noise_filter.36816763587772390949973500490615291253850197844661775345332545699999180859635
Line 255, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/8.uart_noise_filter/latest/run.log

  UVM_ERROR @ 43899764640 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 10,                                 clk_pulses: 0
  UVM_ERROR @ 43899855549 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 43899946458 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (187 [0xbb] vs 254 [0xfe]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 43900037367 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 43900128276 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (187 [0xbb] vs 255 [0xff]) reg name: uart_reg_block.rdata

... and 12 more failures.

Test uart_stress_all_with_rand_reset has 5 failures.

22.uart_stress_all_with_rand_reset.104988501569991797191920746512020220760651773892178374858646344104091326514535
Line 945, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/22.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 85133952404 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 6,                                 clk_pulses: 0
  UVM_ERROR @ 85133972812 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 85133993220 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 253 [0xfd]) reg name: uart_reg_block.rdata
  UVM_INFO @ 85187319324 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 135/791
  UVM_ERROR @ 85228829196 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 11,                                 clk_pulses: 0

41.uart_stress_all_with_rand_reset.78961106697513509273935078816055868684676896852462280666820944167433212334806
Line 1754, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/41.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 426117315801 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 5,                                 clk_pulses: 0
  UVM_ERROR @ 426117357468 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 426117565803 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (106 [0x6a] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 426117607470 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 426117732471 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (106 [0x6a] vs 255 [0xff]) reg name: uart_reg_block.rdata

... and 3 more failures.

Test uart_long_xfer_wo_dly has 1 failures.

25.uart_long_xfer_wo_dly.9760019554227174203688414752429165630608579384368975371823764486526219452561
Line 254, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/25.uart_long_xfer_wo_dly/latest/run.log

  UVM_ERROR @ 69665906555 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 0,                                 clk_pulses: 0
  UVM_ERROR @ 69686553779 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 70679561723 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 70904504699 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
  UVM_ERROR @ 70986623003 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1

UVM_ERROR (uart_scoreboard.sv:374) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 14 failures:

Test uart_noise_filter has 8 failures.

4.uart_noise_filter.80483939646307567026218667381161488526693153148831843995502519039301524657786
Line 256, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/4.uart_noise_filter/latest/run.log

  UVM_ERROR @ 27053981805 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 27053981805 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 27053981805 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 27061377520 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 27451371280 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 17,                                 clk_pulses: 0

17.uart_noise_filter.74023970819710830379788620301112996904952514977854797005102318023690380468812
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/17.uart_noise_filter/latest/run.log

  UVM_ERROR @  67557266 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 377477266 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
  UVM_ERROR @ 377477266 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr
  UVM_ERROR @ 634717266 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 634717266 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1

... and 6 more failures.

Test uart_stress_all_with_rand_reset has 4 failures.

7.uart_stress_all_with_rand_reset.19373322909179568704823919149565959819438113037761110471397129279035834883480
Line 256, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/7.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 364878317 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 364878317 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 364878317 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 414119476 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @ 414119476 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr

10.uart_stress_all_with_rand_reset.92905325330030517459584158329388654654191554840668096682259679678150740163974
Line 307, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/10.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4468010400 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 4468010400 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 4468010400 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 4476041738 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 4497198998 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

... and 2 more failures.

Test uart_stress_all has 2 failures.

24.uart_stress_all.95495869107649637581062724386351440025037321108099596786882425892790438015704
Line 272, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/24.uart_stress_all/latest/run.log

  UVM_ERROR @ 151468235044 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 151468235044 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 151481682108 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 151481682108 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 151615471884 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2,                                 clk_pulses: 0

42.uart_stress_all.24404525909035031712710301149602656086377115319263331620767201400372146797991
Line 271, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/42.uart_stress_all/latest/run.log

  UVM_ERROR @ 204036573377 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 204036573377 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 204069758529 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
  UVM_ERROR @ 204069795566 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 204069832603 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (211 [0xd3] vs 191 [0xbf]) reg name: uart_reg_block.rdata

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxParityErr has 2 failures:

Test uart_stress_all has 1 failures.

36.uart_stress_all.91446714576104843774889760114797542465614312535761511940030791327102719303801
Line 265, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/36.uart_stress_all/latest/run.log

  UVM_ERROR @ 32596832762 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @ 32727755150 ps: (uart_scoreboard.sv:498) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1,                                 clk_pulses: 0
  UVM_ERROR @ 32727765676 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
  UVM_ERROR @ 32727776202 ps: (uart_scoreboard.sv:528) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (184 [0xb8] vs 255 [0xff]) reg name: uart_reg_block.rdata
  UVM_ERROR @ 32771964350 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0

Test uart_stress_all_with_rand_reset has 1 failures.

57.uart_stress_all_with_rand_reset.105280512516669514512313915387856565659795971646991521561804092391105038277916
Line 259, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/57.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 414025629 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
  UVM_ERROR @ 414025629 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
  UVM_ERROR @ 414025629 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
  UVM_ERROR @ 414025629 ps: (uart_scoreboard.sv:444) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr
  UVM_INFO @ 419705629 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/899

UVM_ERROR (uart_scoreboard.sv:442) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxFrameErr has 1 failures:

Test uart_noise_filter has 1 failures.

19.uart_noise_filter.40592524507545494764912492943923293162739167464282111415308880193957818057350
Line 248, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/19.uart_noise_filter/latest/run.log

  UVM_ERROR @  96908861 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
  UVM_ERROR @ 281956449 ps: (uart_scoreboard.sv:374) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
  UVM_ERROR @ 281956449 ps: (uart_scoreboard.sv:390) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
  UVM_ERROR @ 281956449 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
  UVM_ERROR @ 399106031 ps: (uart_scoreboard.sv:442) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr

UVM_ERROR (uart_intr_vseq.sv:312) [uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (* [*] vs * [*]) has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

60.uart_stress_all_with_rand_reset.79306179803171134392539752629028477140643843322242785668943061154798181680655
Line 344, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/60.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 54776622970 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 54899456549 ps: (cip_base_vseq__tl_errors.svh:196) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 27/618
  UVM_ERROR @ 55024790133 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 55308457367 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 55788291660 ps: (uart_intr_vseq.sv:312) [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] Check failed act_intr_state[uart_intr] == exp (1 [0x1] vs 0 [0x0])

UVM_ERROR (uart_scoreboard.sv:537) scoreboard [scoreboard] TX item mismatch! has 1 failures:
- Test uart_stress_all_with_rand_reset has 1 failures.
  - 76.uart_stress_all_with_rand_reset.79141670550066955619018233963906745086067831491430638086553641692434844966515
    Line 667, in log /container/opentitan-public/scratch/os_regression/uart-sim-vcs/76.uart_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 202392690515 ps: (uart_scoreboard.sv:537) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] TX item mismatch!
  exp:
  -----------------------------------
  Name      Type       Size  Value
  -----------------------------------
```