Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : uart_core
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.49 98.94 99.04 96.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.uart_core 98.98 98.94 99.04 97.96 100.00



Module Instance : tb.dut.uart_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.98 98.94 99.04 97.96 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.73 99.70 95.90 99.32 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
intr_hw_rx_break_err 100.00 100.00 100.00 100.00 100.00
intr_hw_rx_frame_err 100.00 100.00 100.00 100.00 100.00
intr_hw_rx_overflow 100.00 100.00 100.00 100.00 100.00
intr_hw_rx_parity_err 100.00 100.00 100.00 100.00 100.00
intr_hw_rx_timeout 100.00 100.00 100.00 100.00 100.00
intr_hw_rx_watermark 100.00 100.00 100.00 100.00 100.00
intr_hw_tx_done 100.00 100.00 100.00 100.00 100.00
intr_hw_tx_empty 94.44 100.00 77.78 100.00 100.00
intr_hw_tx_watermark 94.44 100.00 77.78 100.00 100.00
sync_rx 100.00 100.00 100.00
u_uart_rxfifo 97.22 100.00 88.89 100.00 100.00
u_uart_txfifo 97.22 100.00 88.89 100.00 100.00
uart_rx 100.00 100.00 100.00 100.00
uart_tx 100.00 100.00 100.00 100.00

Line Coverage for Module : uart_core
Line No.TotalCoveredPercent
TOTAL949398.94
CONT_ASSIGN7311100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9511100.00
CONT_ASSIGN9811100.00
ALWAYS10544100.00
ALWAYS11344100.00
ALWAYS12277100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15211100.00
ALWAYS16644100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN17911100.00
CONT_ASSIGN21311100.00
ALWAYS21577100.00
ALWAYS24655100.00
CONT_ASSIGN25511100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN26011100.00
CONT_ASSIGN28011100.00
ALWAYS30244100.00
ALWAYS31444100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32411100.00
ALWAYS32733100.00
ALWAYS3376583.33
CONT_ASSIGN35311100.00
CONT_ASSIGN35411100.00
CONT_ASSIGN35611100.00
CONT_ASSIGN35811100.00
CONT_ASSIGN37611100.00
ALWAYS37955100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN38911100.00
CONT_ASSIGN51211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
73 1 1
74 1 1
75 1 1
76 1 1
77 1 1
79 1 1
80 1 1
81 1 1
82 1 1
84 1 1
85 1 1
94 1 1
95 1 1
98 1 1
105 2 2
106 2 2
MISSING_ELSE
113 1 1
114 1 1
115 1 1
116 1 1
122 2 2
124 1 1
126 2 2
MISSING_ELSE
130 2 2
MISSING_ELSE
140 1 1
142 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
149 1 1
151 1 1
152 1 1
166 1 1
167 1 1
168 1 1
169 1 1
MISSING_ELSE
173 1 1
179 1 1
213 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
220 1 1
222 1 1
246 1 1
247 1 1
248 1 1
250 1 1
251 1 1
255 1 1
258 1 1
260 1 1
280 1 1
302 2 2
303 2 2
MISSING_ELSE
314 1 1
315 1 1
317 1 1
319 1 1
322 1 1
324 1 1
327 1 1
328 1 1
330 1 1
337 1 1
340 0 1
341 1 1
343 1 1
345 1 1
347 1 1
353 1 1
354 1 1
356 1 1
358 1 1
376 1 1
379 1 1
380 1 1
381 1 1
383 1 1
384 1 1
388 1 1
389 1 1
512 1 1


Cond Coverage for Module : uart_core
TotalCoveredPercent
Conditions10410399.04
Logical10410399.04
Non-Logical00
Event00

 LINE       79
 EXPRESSION (reg2hw.fifo_ctrl.rxrst.q & reg2hw.fifo_ctrl.rxrst.qe)
             ------------1-----------   ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T3,T4

 LINE       80
 EXPRESSION (reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe)
             ------------1-----------   ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       94
 EXPRESSION (rx_valid & (((~event_rx_frame_err)) | (rx_fifo_data != 8'b0)))
             ----1---   -------------------------2------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT10,T11,T14
11CoveredT1,T2,T3

 LINE       94
 SUB-EXPRESSION (((~event_rx_frame_err)) | (rx_fifo_data != 8'b0))
                 -----------1-----------   -----------2----------
-1--2-StatusTests
00CoveredT10,T11,T14
01CoveredT1,T7,T10
10CoveredT1,T2,T3

 LINE       94
 SUB-EXPRESSION (rx_fifo_data != 8'b0)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       95
 EXPRESSION (event_rx_frame_err & (rx_fifo_data == 8'b0))
             ---------1--------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T7,T10
11CoveredT10,T11,T14

 LINE       95
 SUB-EXPRESSION (rx_fifo_data == 8'b0)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       98
 EXPRESSION (((break_st_q == BRK_WAIT) || not_allzero_char) ? 5'b0 : (allzero_err ? ((allzero_cnt_q + 5'b1)) : allzero_cnt_q))
             -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       98
 SUB-EXPRESSION ((break_st_q == BRK_WAIT) || not_allzero_char)
                 ------------1-----------    --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT10,T11,T14

 LINE       98
 SUB-EXPRESSION (break_st_q == BRK_WAIT)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T14

 LINE       98
 SUB-EXPRESSION (allzero_err ? ((allzero_cnt_q + 5'b1)) : allzero_cnt_q)
                 -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T14

 LINE       146
 EXPRESSION (tx_uart_idle & ((~tx_fifo_rvalid)))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT2,T4,T5
10CoveredT2,T4,T5
11CoveredT1,T2,T3

 LINE       168
 EXPRESSION (tx_enable || rx_enable)
             ----1----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T4,T5

 LINE       179
 EXPRESSION (tx_uart_idle & tx_fifo_rvalid & tx_enable)
             ------1-----   -------2------   ----3----
-1--2--3-StatusTests
011CoveredT2,T4,T5
101CoveredT1,T2,T3
110CoveredT2,T4,T5
111CoveredT2,T4,T5

 LINE       200
 EXPRESSION (((^tx_fifo_data)) ^ reg2hw.ctrl.parity_odd.q)
             --------1--------   ------------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11CoveredT2,T4,T5

 LINE       213
 EXPRESSION (line_loopback ? rx : tx_out_q)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T16,T17

 LINE       255
 EXPRESSION ((rx_sync & rx_sync_q1) | (rx_sync & rx_sync_q2) | (rx_sync_q1 & rx_sync_q2))
             -----------1----------   -----------2----------   ------------3------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       255
 SUB-EXPRESSION (rx_sync & rx_sync_q1)
                 ---1---   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       255
 SUB-EXPRESSION (rx_sync & rx_sync_q2)
                 ---1---   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       255
 SUB-EXPRESSION (rx_sync_q1 & rx_sync_q2)
                 -----1----   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       258
 EXPRESSION (rxnf_enable ? rx_in_maj : rx_sync)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       260
 EXPRESSION (sys_loopback ? tx_out : (line_loopback ? 1'b1 : rx_in_mx))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T16,T17

 LINE       260
 SUB-EXPRESSION (line_loopback ? 1'b1 : rx_in_mx)
                 ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T16,T17

 LINE       280
 EXPRESSION (rx_valid & ((~event_rx_frame_err)) & ((~event_rx_parity_err)))
             ----1---   -----------2-----------   ------------3-----------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T7,T10
110CoveredT3,T7,T11
111CoveredT1,T2,T3

 LINE       322
 EXPRESSION (tx_fifo_depth == '0)
            ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       324
 EXPRESSION (((~tx_fifo_rvalid)) & ((~tx_uart_idle_q)) & tx_uart_idle)
             ---------1---------   ---------2---------   ------3-----
-1--2--3-StatusTests
011CoveredT2,T4,T5
101CoveredT1,T2,T3
110CoveredT2,T4,T5
111CoveredT2,T4,T5

 LINE       341
 EXPRESSION (uart_fifo_rxilvl == (RxFifoDepthW - 1))
            --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T5

 LINE       356
 EXPRESSION (rx_fifo_depth != rx_fifo_depth_prev_q)
            -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (uart_rxto_en == 1'b0) ? 24'b0 : (event_rx_timeout ? 24'b0 : (rx_fifo_depth_changed ? 24'b0 : ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       358
 SUB-EXPRESSION (uart_rxto_en == 1'b0)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       358
 SUB-EXPRESSION 
 Number  Term
      1  event_rx_timeout ? 24'b0 : (rx_fifo_depth_changed ? 24'b0 : ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T10,T12

 LINE       358
 SUB-EXPRESSION (rx_fifo_depth_changed ? 24'b0 : ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q)))
                 ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T5

 LINE       358
 SUB-EXPRESSION ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q))
                 ----------1----------
-1-StatusTests
0CoveredT2,T4,T5
1CoveredT1,T2,T3

 LINE       358
 SUB-EXPRESSION (rx_fifo_depth == '0)
                ----------1----------
-1-StatusTests
0CoveredT2,T4,T5
1CoveredT1,T2,T3

 LINE       358
 SUB-EXPRESSION (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q)
                 ------1-----
-1-StatusTests
0CoveredT2,T4,T5
1CoveredT2,T4,T5

 LINE       376
 EXPRESSION ((rx_timeout_count_q == uart_rxto_val) & uart_rxto_en)
             ------------------1------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T10,T12

 LINE       376
 SUB-EXPRESSION (rx_timeout_count_q == uart_rxto_val)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       388
 EXPRESSION (rx_fifo_wvalid & ((~rx_fifo_wready)))
             -------1------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT5,T11,T14

 LINE       389
 EXPRESSION (break_err & (break_st_q == BRK_CHK))
             ----1----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT10,T11,T14

 LINE       389
 SUB-EXPRESSION (break_st_q == BRK_CHK)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : uart_core
Line No.TotalCoveredPercent
Branches 50 48 96.00
TERNARY 98 3 3 100.00
TERNARY 213 2 2 100.00
TERNARY 258 2 2 100.00
TERNARY 260 3 3 100.00
TERNARY 358 6 6 100.00
IF 105 3 3 100.00
CASE 113 4 4 100.00
IF 122 6 5 83.33
IF 166 3 3 100.00
IF 215 4 4 100.00
IF 246 2 2 100.00
IF 302 3 3 100.00
IF 314 2 2 100.00
IF 327 2 2 100.00
IF 337 3 2 66.67
IF 379 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 98 (((break_st_q == BRK_WAIT) || not_allzero_char)) ? -2-: 98 (allzero_err) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T10,T11,T14
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 213 (line_loopback) ?

Branches:
-1-StatusTests
1 Covered T15,T16,T17
0 Covered T1,T2,T3


LineNo. Expression -1-: 258 (rxnf_enable) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 260 (sys_loopback) ? -2-: 260 (line_loopback) ?

Branches:
-1--2-StatusTests
1 - Covered T15,T16,T17
0 1 Covered T15,T16,T17
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 358 ((uart_rxto_en == 1'b0)) ? -2-: 358 (event_rx_timeout) ? -3-: 358 (rx_fifo_depth_changed) ? -4-: 358 ((rx_fifo_depth == '0)) ? -5-: 358 (rx_tick_baud) ?

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T4,T10,T12
0 0 1 - - Covered T2,T4,T5
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T2,T4,T5
0 0 0 0 0 Covered T2,T4,T5


LineNo. Expression -1-: 105 if ((!rst_ni)) -2-: 106 if (rx_enable)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 113 case (reg2hw.ctrl.rxblvl.q)

Branches:
-1-StatusTests
2'h0 Covered T1,T2,T3
2'h1 Covered T1,T2,T3
2'h2 Covered T1,T2,T3
default Covered T1,T3,T5


LineNo. Expression -1-: 122 if ((!rst_ni)) -2-: 124 case (break_st_q) -3-: 126 if (event_rx_break_err) -4-: 130 if (rx_in)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 BRK_CHK 1 - Covered T10,T11,T14
0 BRK_CHK 0 - Covered T1,T2,T3
0 BRK_WAIT - 1 Covered T10,T11,T14
0 BRK_WAIT - 0 Covered T10,T11,T14
0 default - - Not Covered


LineNo. Expression -1-: 166 if ((!rst_ni)) -2-: 168 if ((tx_enable || rx_enable))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 215 if ((!rst_ni)) -2-: 217 if (ovrd_tx_en) -3-: 219 if (sys_loopback)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T6,T9,T13
0 0 1 Covered T15,T16,T17
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 246 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 302 if ((!rst_ni)) -2-: 303 if (tick_baud_x16)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 314 if ((uart_fifo_txilvl >= (TxFifoDepthW - 2)))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 327 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 337 if ((uart_fifo_rxilvl > (RxFifoDepthW - 1))) -2-: 341 if ((uart_fifo_rxilvl == (RxFifoDepthW - 1)))

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T2,T4,T5
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 379 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : uart_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
RxFifoDepth_A 1060 1060 0 0
TxFifoDepth_A 1060 1060 0 0


RxFifoDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1060 1060 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

TxFifoDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1060 1060 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.uart_core
Line No.TotalCoveredPercent
TOTAL949398.94
CONT_ASSIGN7311100.00
CONT_ASSIGN7411100.00
CONT_ASSIGN7511100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9511100.00
CONT_ASSIGN9811100.00
ALWAYS10544100.00
ALWAYS11344100.00
ALWAYS12277100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN14711100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15211100.00
ALWAYS16644100.00
CONT_ASSIGN17311100.00
CONT_ASSIGN17911100.00
CONT_ASSIGN21311100.00
ALWAYS21577100.00
ALWAYS24655100.00
CONT_ASSIGN25511100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN26011100.00
CONT_ASSIGN28011100.00
ALWAYS30244100.00
ALWAYS31444100.00
CONT_ASSIGN32211100.00
CONT_ASSIGN32411100.00
ALWAYS32733100.00
ALWAYS3376583.33
CONT_ASSIGN35311100.00
CONT_ASSIGN35411100.00
CONT_ASSIGN35611100.00
CONT_ASSIGN35811100.00
CONT_ASSIGN37611100.00
ALWAYS37955100.00
CONT_ASSIGN38811100.00
CONT_ASSIGN38911100.00
CONT_ASSIGN51211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
73 1 1
74 1 1
75 1 1
76 1 1
77 1 1
79 1 1
80 1 1
81 1 1
82 1 1
84 1 1
85 1 1
94 1 1
95 1 1
98 1 1
105 2 2
106 2 2
MISSING_ELSE
113 1 1
114 1 1
115 1 1
116 1 1
122 2 2
124 1 1
126 2 2
MISSING_ELSE
130 2 2
MISSING_ELSE
140 1 1
142 1 1
144 1 1
145 1 1
146 1 1
147 1 1
148 1 1
149 1 1
151 1 1
152 1 1
166 1 1
167 1 1
168 1 1
169 1 1
MISSING_ELSE
173 1 1
179 1 1
213 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
220 1 1
222 1 1
246 1 1
247 1 1
248 1 1
250 1 1
251 1 1
255 1 1
258 1 1
260 1 1
280 1 1
302 2 2
303 2 2
MISSING_ELSE
314 1 1
315 1 1
317 1 1
319 1 1
322 1 1
324 1 1
327 1 1
328 1 1
330 1 1
337 1 1
340 0 1
341 1 1
343 1 1
345 1 1
347 1 1
353 1 1
354 1 1
356 1 1
358 1 1
376 1 1
379 1 1
380 1 1
381 1 1
383 1 1
384 1 1
388 1 1
389 1 1
512 1 1


Cond Coverage for Instance : tb.dut.uart_core
TotalCoveredPercent
Conditions10410399.04
Logical10410399.04
Non-Logical00
Event00

 LINE       79
 EXPRESSION (reg2hw.fifo_ctrl.rxrst.q & reg2hw.fifo_ctrl.rxrst.qe)
             ------------1-----------   ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T3,T4

 LINE       80
 EXPRESSION (reg2hw.fifo_ctrl.txrst.q & reg2hw.fifo_ctrl.txrst.qe)
             ------------1-----------   ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT2,T3,T4

 LINE       94
 EXPRESSION (rx_valid & (((~event_rx_frame_err)) | (rx_fifo_data != 8'b0)))
             ----1---   -------------------------2------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT10,T11,T14
11CoveredT1,T2,T3

 LINE       94
 SUB-EXPRESSION (((~event_rx_frame_err)) | (rx_fifo_data != 8'b0))
                 -----------1-----------   -----------2----------
-1--2-StatusTests
00CoveredT10,T11,T14
01CoveredT1,T7,T10
10CoveredT1,T2,T3

 LINE       94
 SUB-EXPRESSION (rx_fifo_data != 8'b0)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       95
 EXPRESSION (event_rx_frame_err & (rx_fifo_data == 8'b0))
             ---------1--------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T7,T10
11CoveredT10,T11,T14

 LINE       95
 SUB-EXPRESSION (rx_fifo_data == 8'b0)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       98
 EXPRESSION (((break_st_q == BRK_WAIT) || not_allzero_char) ? 5'b0 : (allzero_err ? ((allzero_cnt_q + 5'b1)) : allzero_cnt_q))
             -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       98
 SUB-EXPRESSION ((break_st_q == BRK_WAIT) || not_allzero_char)
                 ------------1-----------    --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT10,T11,T14

 LINE       98
 SUB-EXPRESSION (break_st_q == BRK_WAIT)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T14

 LINE       98
 SUB-EXPRESSION (allzero_err ? ((allzero_cnt_q + 5'b1)) : allzero_cnt_q)
                 -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT10,T11,T14

 LINE       146
 EXPRESSION (tx_uart_idle & ((~tx_fifo_rvalid)))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT2,T4,T5
10CoveredT2,T4,T5
11CoveredT1,T2,T3

 LINE       168
 EXPRESSION (tx_enable || rx_enable)
             ----1----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T4,T5

 LINE       179
 EXPRESSION (tx_uart_idle & tx_fifo_rvalid & tx_enable)
             ------1-----   -------2------   ----3----
-1--2--3-StatusTests
011CoveredT2,T4,T5
101CoveredT1,T2,T3
110CoveredT2,T4,T5
111CoveredT2,T4,T5

 LINE       200
 EXPRESSION (((^tx_fifo_data)) ^ reg2hw.ctrl.parity_odd.q)
             --------1--------   ------------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT4,T5,T6
11CoveredT2,T4,T5

 LINE       213
 EXPRESSION (line_loopback ? rx : tx_out_q)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T16,T17

 LINE       255
 EXPRESSION ((rx_sync & rx_sync_q1) | (rx_sync & rx_sync_q2) | (rx_sync_q1 & rx_sync_q2))
             -----------1----------   -----------2----------   ------------3------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3

 LINE       255
 SUB-EXPRESSION (rx_sync & rx_sync_q1)
                 ---1---   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       255
 SUB-EXPRESSION (rx_sync & rx_sync_q2)
                 ---1---   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       255
 SUB-EXPRESSION (rx_sync_q1 & rx_sync_q2)
                 -----1----   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       258
 EXPRESSION (rxnf_enable ? rx_in_maj : rx_sync)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       260
 EXPRESSION (sys_loopback ? tx_out : (line_loopback ? 1'b1 : rx_in_mx))
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T16,T17

 LINE       260
 SUB-EXPRESSION (line_loopback ? 1'b1 : rx_in_mx)
                 ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T16,T17

 LINE       280
 EXPRESSION (rx_valid & ((~event_rx_frame_err)) & ((~event_rx_parity_err)))
             ----1---   -----------2-----------   ------------3-----------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T7,T10
110CoveredT3,T7,T11
111CoveredT1,T2,T3

 LINE       322
 EXPRESSION (tx_fifo_depth == '0)
            ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       324
 EXPRESSION (((~tx_fifo_rvalid)) & ((~tx_uart_idle_q)) & tx_uart_idle)
             ---------1---------   ---------2---------   ------3-----
-1--2--3-StatusTests
011CoveredT2,T4,T5
101CoveredT1,T2,T3
110CoveredT2,T4,T5
111CoveredT2,T4,T5

 LINE       341
 EXPRESSION (uart_fifo_rxilvl == (RxFifoDepthW - 1))
            --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T5

 LINE       356
 EXPRESSION (rx_fifo_depth != rx_fifo_depth_prev_q)
            -------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       358
 EXPRESSION 
 Number  Term
      1  (uart_rxto_en == 1'b0) ? 24'b0 : (event_rx_timeout ? 24'b0 : (rx_fifo_depth_changed ? 24'b0 : ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       358
 SUB-EXPRESSION (uart_rxto_en == 1'b0)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       358
 SUB-EXPRESSION 
 Number  Term
      1  event_rx_timeout ? 24'b0 : (rx_fifo_depth_changed ? 24'b0 : ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T10,T12

 LINE       358
 SUB-EXPRESSION (rx_fifo_depth_changed ? 24'b0 : ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q)))
                 ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T5

 LINE       358
 SUB-EXPRESSION ((rx_fifo_depth == '0) ? 24'b0 : (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q))
                 ----------1----------
-1-StatusTests
0CoveredT2,T4,T5
1CoveredT1,T2,T3

 LINE       358
 SUB-EXPRESSION (rx_fifo_depth == '0)
                ----------1----------
-1-StatusTests
0CoveredT2,T4,T5
1CoveredT1,T2,T3

 LINE       358
 SUB-EXPRESSION (rx_tick_baud ? ((rx_timeout_count_q + 24'b1)) : rx_timeout_count_q)
                 ------1-----
-1-StatusTests
0CoveredT2,T4,T5
1CoveredT2,T4,T5

 LINE       376
 EXPRESSION ((rx_timeout_count_q == uart_rxto_val) & uart_rxto_en)
             ------------------1------------------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT4,T10,T12

 LINE       376
 SUB-EXPRESSION (rx_timeout_count_q == uart_rxto_val)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       388
 EXPRESSION (rx_fifo_wvalid & ((~rx_fifo_wready)))
             -------1------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT5,T11,T14

 LINE       389
 EXPRESSION (break_err & (break_st_q == BRK_CHK))
             ----1----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT10,T11,T14

 LINE       389
 SUB-EXPRESSION (break_st_q == BRK_CHK)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.uart_core
Line No.TotalCoveredPercent
Branches 49 48 97.96
TERNARY 98 3 3 100.00
TERNARY 213 2 2 100.00
TERNARY 258 2 2 100.00
TERNARY 260 3 3 100.00
TERNARY 358 6 6 100.00
IF 105 3 3 100.00
CASE 113 4 4 100.00
IF 122 5 5 100.00
IF 166 3 3 100.00
IF 215 4 4 100.00
IF 246 2 2 100.00
IF 302 3 3 100.00
IF 314 2 2 100.00
IF 327 2 2 100.00
IF 337 3 2 66.67
IF 379 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 98 (((break_st_q == BRK_WAIT) || not_allzero_char)) ? -2-: 98 (allzero_err) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T10,T11,T14
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 213 (line_loopback) ?

Branches:
-1-StatusTests
1 Covered T15,T16,T17
0 Covered T1,T2,T3


LineNo. Expression -1-: 258 (rxnf_enable) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 260 (sys_loopback) ? -2-: 260 (line_loopback) ?

Branches:
-1--2-StatusTests
1 - Covered T15,T16,T17
0 1 Covered T15,T16,T17
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 358 ((uart_rxto_en == 1'b0)) ? -2-: 358 (event_rx_timeout) ? -3-: 358 (rx_fifo_depth_changed) ? -4-: 358 ((rx_fifo_depth == '0)) ? -5-: 358 (rx_tick_baud) ?

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T4,T10,T12
0 0 1 - - Covered T2,T4,T5
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T2,T4,T5
0 0 0 0 0 Covered T2,T4,T5


LineNo. Expression -1-: 105 if ((!rst_ni)) -2-: 106 if (rx_enable)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 113 case (reg2hw.ctrl.rxblvl.q)

Branches:
-1-StatusTests
2'h0 Covered T1,T2,T3
2'h1 Covered T1,T2,T3
2'h2 Covered T1,T2,T3
default Covered T1,T3,T5


LineNo. Expression -1-: 122 if ((!rst_ni)) -2-: 124 case (break_st_q) -3-: 126 if (event_rx_break_err) -4-: 130 if (rx_in)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 BRK_CHK 1 - Covered T10,T11,T14
0 BRK_CHK 0 - Covered T1,T2,T3
0 BRK_WAIT - 1 Covered T10,T11,T14
0 BRK_WAIT - 0 Covered T10,T11,T14
0 default - - Excluded


LineNo. Expression -1-: 166 if ((!rst_ni)) -2-: 168 if ((tx_enable || rx_enable))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 215 if ((!rst_ni)) -2-: 217 if (ovrd_tx_en) -3-: 219 if (sys_loopback)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T6,T9,T13
0 0 1 Covered T15,T16,T17
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 246 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 302 if ((!rst_ni)) -2-: 303 if (tick_baud_x16)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 314 if ((uart_fifo_txilvl >= (TxFifoDepthW - 2)))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 327 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 337 if ((uart_fifo_rxilvl > (RxFifoDepthW - 1))) -2-: 341 if ((uart_fifo_rxilvl == (RxFifoDepthW - 1)))

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T2,T4,T5
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 379 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.uart_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
RxFifoDepth_A 1060 1060 0 0
TxFifoDepth_A 1060 1060 0 0


RxFifoDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1060 1060 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

TxFifoDepth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1060 1060 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%