Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : uart
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.02 99.10 97.65 100.00 98.38 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_reg 99.06 98.77 98.68 100.00 97.85 100.00
uart_core 98.73 99.70 95.90 99.32 100.00
uart_csr_assert 100.00 100.00

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : uart
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN7811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv' or '../src/lowrisc_ip_uart_0.1/rtl/uart.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
78 1 1

Cond Coverage for Module : uart
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       78
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------
-1--2-StatusTests
01CoveredT21,T22,T23
10CoveredT1,T2,T3
11CoveredT21,T22,T23
Toggle Coverage for Module : uart
TotalCoveredPercent
Totals 37 37 100.00
Total Bits 354 354 100.00
Total Bits 0->1 177 177 100.00
Total Bits 1->0 177 177 100.00

Ports 37 37 100.00
Port Bits 354 354 100.00
Port Bits 0->1 177 177 100.00
Port Bits 1->0 177 177 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T10,T20,T15 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T10,T18,T19 Yes T10,T18,T19 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T21,T24,T25 Yes T21,T24,T25 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T21,T24,T25 Yes T21,T24,T25 OUTPUT
cio_rx_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
cio_tx_o Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
intr_tx_empty_o Yes Yes T1,T2,T5 Yes T1,T2,T5 OUTPUT
intr_rx_watermark_o Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT
intr_tx_done_o Yes Yes T1,T5,T6 Yes T1,T5,T6 OUTPUT
intr_rx_overflow_o Yes Yes T10,T13,T17 Yes T10,T13,T17 OUTPUT
intr_rx_frame_err_o Yes Yes T10,T14,T15 Yes T10,T14,T15 OUTPUT
intr_rx_break_err_o Yes Yes T10,T13,T12 Yes T10,T13,T12 OUTPUT
intr_rx_timeout_o Yes Yes T9,T10,T15 Yes T9,T10,T15 OUTPUT
intr_rx_parity_err_o Yes Yes T10,T16,T13 Yes T10,T16,T13 OUTPUT

*Tests covering at least one bit in the range
Assert Coverage for Module : uart
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertsKnown_A 2147483647 2147483647 0 0
FpvSecCmRegWeOnehotCheck_A 2147483647 80 0 0
RxBreakErrKnown_A 2147483647 2147483647 0 0
RxFrameErrKnown_A 2147483647 2147483647 0 0
RxOverflowKnown_A 2147483647 2147483647 0 0
RxParityErrKnown_A 2147483647 2147483647 0 0
RxTimeoutKnown_A 2147483647 2147483647 0 0
RxWatermarkKnown_A 2147483647 2147483647 0 0
TxDoneKnown_A 2147483647 2147483647 0 0
TxEmptyKnown_A 2147483647 2147483647 0 0
TxEnIsOne_A 2147483647 2147483647 0 0
TxKnown_A 2147483647 2147483647 0 0
TxWatermarkKnown_A 2147483647 2147483647 0 0


AlertsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 385781 385718 0 0
T2 26211 26149 0 0
T3 27426 27367 0 0
T4 30893 30795 0 0
T5 114768 114767 0 0
T6 301786 301724 0 0
T7 150607 150607 0 0
T8 102353 102344 0 0
T9 226205 226197 0 0
T10 541572 541561 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 80 0 0
T24 6253 20 0 0
T25 0 20 0 0
T26 0 10 0 0
T86 0 10 0 0
T87 0 20 0 0
T88 311076 0 0 0
T89 646074 0 0 0
T90 853835 0 0 0
T91 360684 0 0 0
T92 892071 0 0 0
T93 628371 0 0 0
T94 147385 0 0 0
T95 87896 0 0 0
T96 345219 0 0 0

RxBreakErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 385781 385718 0 0
T2 26211 26149 0 0
T3 27426 27367 0 0
T4 30893 30795 0 0
T5 114768 114767 0 0
T6 301786 301724 0 0
T7 150607 150607 0 0
T8 102353 102344 0 0
T9 226205 226197 0 0
T10 541572 541561 0 0

RxFrameErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 385781 385718 0 0
T2 26211 26149 0 0
T3 27426 27367 0 0
T4 30893 30795 0 0
T5 114768 114767 0 0
T6 301786 301724 0 0
T7 150607 150607 0 0
T8 102353 102344 0 0
T9 226205 226197 0 0
T10 541572 541561 0 0

RxOverflowKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 385781 385718 0 0
T2 26211 26149 0 0
T3 27426 27367 0 0
T4 30893 30795 0 0
T5 114768 114767 0 0
T6 301786 301724 0 0
T7 150607 150607 0 0
T8 102353 102344 0 0
T9 226205 226197 0 0
T10 541572 541561 0 0

RxParityErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 385781 385718 0 0
T2 26211 26149 0 0
T3 27426 27367 0 0
T4 30893 30795 0 0
T5 114768 114767 0 0
T6 301786 301724 0 0
T7 150607 150607 0 0
T8 102353 102344 0 0
T9 226205 226197 0 0
T10 541572 541561 0 0

RxTimeoutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 385781 385718 0 0
T2 26211 26149 0 0
T3 27426 27367 0 0
T4 30893 30795 0 0
T5 114768 114767 0 0
T6 301786 301724 0 0
T7 150607 150607 0 0
T8 102353 102344 0 0
T9 226205 226197 0 0
T10 541572 541561 0 0

RxWatermarkKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 385781 385718 0 0
T2 26211 26149 0 0
T3 27426 27367 0 0
T4 30893 30795 0 0
T5 114768 114767 0 0
T6 301786 301724 0 0
T7 150607 150607 0 0
T8 102353 102344 0 0
T9 226205 226197 0 0
T10 541572 541561 0 0

TxDoneKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 385781 385718 0 0
T2 26211 26149 0 0
T3 27426 27367 0 0
T4 30893 30795 0 0
T5 114768 114767 0 0
T6 301786 301724 0 0
T7 150607 150607 0 0
T8 102353 102344 0 0
T9 226205 226197 0 0
T10 541572 541561 0 0

TxEmptyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 385781 385718 0 0
T2 26211 26149 0 0
T3 27426 27367 0 0
T4 30893 30795 0 0
T5 114768 114767 0 0
T6 301786 301724 0 0
T7 150607 150607 0 0
T8 102353 102344 0 0
T9 226205 226197 0 0
T10 541572 541561 0 0

TxEnIsOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 385781 385718 0 0
T2 26211 26149 0 0
T3 27426 27367 0 0
T4 30893 30795 0 0
T5 114768 114767 0 0
T6 301786 301724 0 0
T7 150607 150607 0 0
T8 102353 102344 0 0
T9 226205 226197 0 0
T10 541572 541561 0 0

TxKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 385781 385718 0 0
T2 26211 26149 0 0
T3 27426 27367 0 0
T4 30893 30795 0 0
T5 114768 114767 0 0
T6 301786 301724 0 0
T7 150607 150607 0 0
T8 102353 102344 0 0
T9 226205 226197 0 0
T10 541572 541561 0 0

TxWatermarkKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 385781 385718 0 0
T2 26211 26149 0 0
T3 27426 27367 0 0
T4 30893 30795 0 0
T5 114768 114767 0 0
T6 301786 301724 0 0
T7 150607 150607 0 0
T8 102353 102344 0 0
T9 226205 226197 0 0
T10 541572 541561 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%