Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	15527218	0	0
ctrl_rd_A	2147483647	253530	0	0
intr_enable_rd_A	2147483647	225262	0	0
ovrd_rd_A	2147483647	254776	0	0
timeout_ctrl_rd_A	2147483647	253466	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15527218	0	0
T10	541572	141156	0	0
T11	33009	0	0	0
T14	419019	0	0	0
T15	169428	0	0	0
T18	0	82049	0	0
T19	0	248338	0	0
T20	130063	0	0	0
T21	976	0	0	0
T27	204972	0	0	0
T28	0	48296	0	0
T29	0	227197	0	0
T30	0	335844	0	0
T31	0	34172	0	0
T32	0	139930	0	0
T33	0	63378	0	0
T34	0	185746	0	0
T35	708115	0	0	0
T36	409818	0	0	0
T37	445002	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	253530	0	0
T10	541572	15259	0	0
T11	33009	0	0	0
T14	419019	0	0	0
T15	169428	0	0	0
T20	130063	0	0	0
T21	976	0	0	0
T27	204972	0	0	0
T31	0	1655	0	0
T35	708115	0	0	0
T36	409818	0	0	0
T37	445002	0	0	0
T51	0	10413	0	0
T52	0	11772	0	0
T54	0	18514	0	0
T97	0	3164	0	0
T98	0	4096	0	0
T99	0	9630	0	0
T100	0	4089	0	0
T101	0	16121	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	225262	0	0
T10	541572	13977	0	0
T11	33009	0	0	0
T14	419019	0	0	0
T15	169428	0	0	0
T20	130063	0	0	0
T21	976	0	0	0
T27	204972	0	0	0
T31	0	1633	0	0
T35	708115	0	0	0
T36	409818	0	0	0
T37	445002	0	0	0
T51	0	9609	0	0
T52	0	10390	0	0
T54	0	16357	0	0
T97	0	2533	0	0
T98	0	3864	0	0
T99	0	8408	0	0
T102	0	30	0	0
T103	0	2	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	254776	0	0
T10	541572	15323	0	0
T11	33009	0	0	0
T14	419019	0	0	0
T15	169428	0	0	0
T20	130063	0	0	0
T21	976	0	0	0
T27	204972	0	0	0
T31	0	1857	0	0
T35	708115	0	0	0
T36	409818	0	0	0
T37	445002	0	0	0
T51	0	10333	0	0
T52	0	12157	0	0
T54	0	18583	0	0
T97	0	3189	0	0
T98	0	4302	0	0
T99	0	9787	0	0
T100	0	4012	0	0
T101	0	16473	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	253466	0	0
T10	541572	15347	0	0
T11	33009	0	0	0
T14	419019	0	0	0
T15	169428	0	0	0
T20	130063	0	0	0
T21	976	0	0	0
T27	204972	0	0	0
T31	0	1716	0	0
T35	708115	0	0	0
T36	409818	0	0	0
T37	445002	0	0	0
T51	0	10667	0	0
T52	0	11965	0	0
T54	0	17793	0	0
T97	0	3340	0	0
T98	0	4165	0	0
T99	0	9897	0	0
T100	0	4091	0	0
T101	0	16334	0	0