Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	57676627	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

13193876

1

T1

13

T2

21

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	69700495	1			T1	784		T2	793		T3	1
values[0x0]	567271	1			T1	6		T2	22		T4	1
values[0x1]	602737	1			T1	7		T2	25		T4	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39905023	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

30965480

1

T1

285

T2

286

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	291769	1			T2	1		T6	1		T11	1
valid_sources[0x01]	272648	1			T2	3		T10	1		T11	2
valid_sources[0x02]	284493	1			T2	2		T6	1		T11	1
valid_sources[0x03]	243966	1			T2	5		T5	3		T6	1
valid_sources[0x04]	237156	1			T2	1		T6	2		T10	1
valid_sources[0x05]	278174	1			T6	1		T11	3		T12	18
valid_sources[0x06]	260205	1			T2	1		T5	29		T6	3
valid_sources[0x07]	272392	1			T2	6		T6	1		T10	3
valid_sources[0x08]	246656	1			T2	1		T6	2		T10	1
valid_sources[0x09]	244271	1			T2	2		T6	3		T10	3
valid_sources[0x0a]	348373	1			T2	1		T5	2		T10	1
valid_sources[0x0b]	254938	1			T5	17		T6	1		T10	9
valid_sources[0x0c]	251427	1			T2	3		T6	1		T10	1
valid_sources[0x0d]	273694	1			T2	2		T24	11		T13	43
valid_sources[0x0e]	259253	1			T2	7		T5	12		T6	1
valid_sources[0x0f]	321381	1			T2	9		T4	1		T5	26
valid_sources[0x10]	254115	1			T5	1		T6	1		T10	7
valid_sources[0x11]	285387	1			T10	1		T11	2		T24	6
valid_sources[0x12]	301866	1			T2	9		T6	1		T10	5
valid_sources[0x13]	250106	1			T6	2		T10	1		T11	1
valid_sources[0x14]	255562	1			T2	1		T10	3		T24	8
valid_sources[0x15]	256914	1			T2	5		T6	1		T10	2
valid_sources[0x16]	253376	1			T2	3		T11	2		T24	6
valid_sources[0x17]	263108	1			T2	2		T6	2		T9	1
valid_sources[0x18]	255734	1			T5	42		T6	1		T10	1
valid_sources[0x19]	270607	1			T11	2		T24	7		T13	51
valid_sources[0x1a]	279831	1			T2	2		T8	3		T11	2
valid_sources[0x1b]	342620	1			T2	2		T11	2		T24	9
valid_sources[0x1c]	321241	1			T6	3		T10	1		T11	3
valid_sources[0x1d]	249962	1			T5	28		T10	5		T11	2
valid_sources[0x1e]	250159	1			T2	11		T6	1		T10	1
valid_sources[0x1f]	252189	1			T2	1		T5	2		T9	1
valid_sources[0x20]	293788	1			T2	2		T6	2		T11	1
valid_sources[0x21]	263069	1			T2	1		T9	2		T10	2
valid_sources[0x22]	303420	1			T2	3		T8	3		T11	1
valid_sources[0x23]	263473	1			T2	9		T6	1		T10	5
valid_sources[0x24]	261220	1			T2	1		T6	2		T24	5
valid_sources[0x25]	252166	1			T2	2		T5	2		T6	1
valid_sources[0x26]	348208	1			T2	11		T10	1		T11	2
valid_sources[0x27]	270757	1			T2	9		T10	4		T12	5
valid_sources[0x28]	271817	1			T2	7		T6	3		T24	6
valid_sources[0x29]	257338	1			T2	10		T5	16		T6	1
valid_sources[0x2a]	260618	1			T2	5		T20	1		T24	14
valid_sources[0x2b]	291470	1			T2	4		T11	3		T20	9549
valid_sources[0x2c]	352427	1			T2	2		T5	4		T6	1
valid_sources[0x2d]	266401	1			T2	5		T10	4		T11	1
valid_sources[0x2e]	268756	1			T6	2		T12	3		T24	7
valid_sources[0x2f]	260445	1			T2	6		T5	5		T11	2
valid_sources[0x30]	323244	1			T2	3		T5	6		T6	1
valid_sources[0x31]	276797	1			T2	1		T10	2		T11	3
valid_sources[0x32]	255387	1			T2	8		T6	3		T10	2
valid_sources[0x33]	264883	1			T2	3		T10	7		T11	4
valid_sources[0x34]	282263	1			T2	13		T6	3		T11	1
valid_sources[0x35]	364229	1			T2	2		T6	2		T10	1
valid_sources[0x36]	248046	1			T2	4		T8	1		T9	1
valid_sources[0x37]	252118	1			T2	2		T6	3		T10	2
valid_sources[0x38]	269219	1			T11	3		T12	34		T24	5
valid_sources[0x39]	265033	1			T2	8		T10	6		T11	3
valid_sources[0x3a]	242210	1			T6	1		T11	2		T24	7
valid_sources[0x3b]	255562	1			T2	5		T24	4		T13	46
valid_sources[0x3c]	267806	1			T1	688		T2	2		T11	1
valid_sources[0x3d]	266805	1			T2	2		T5	3		T6	1
valid_sources[0x3e]	334182	1			T2	5		T6	1		T10	2
valid_sources[0x3f]	289620	1			T2	3		T6	3		T10	3
valid_sources[0x40]	320836	1			T2	8		T5	20		T10	3
valid_sources[0x41]	266734	1			T2	3		T6	2		T10	4
valid_sources[0x42]	362741	1			T2	2		T6	1		T11	1
valid_sources[0x43]	248119	1			T2	4		T6	1		T11	2
valid_sources[0x44]	300205	1			T6	1		T11	3		T12	11
valid_sources[0x45]	248423	1			T10	2		T11	1		T12	14
valid_sources[0x46]	263659	1			T2	3		T5	21		T6	2
valid_sources[0x47]	303464	1			T2	1		T5	9		T10	1
valid_sources[0x48]	262487	1			T2	3		T6	1		T9	1
valid_sources[0x49]	249862	1			T2	1		T6	1		T11	4
valid_sources[0x4a]	344771	1			T2	1		T9	1		T11	8
valid_sources[0x4b]	262432	1			T2	3		T5	4		T11	1
valid_sources[0x4c]	267003	1			T9	1		T11	4		T24	7
valid_sources[0x4d]	274365	1			T2	18		T6	3		T10	5
valid_sources[0x4e]	288251	1			T2	5		T6	2		T11	2
valid_sources[0x4f]	254451	1			T6	1		T11	1		T24	9
valid_sources[0x50]	258730	1			T2	3		T5	3		T6	2
valid_sources[0x51]	268666	1			T11	1		T12	1		T24	6
valid_sources[0x52]	257837	1			T2	4		T9	1		T10	2
valid_sources[0x53]	262942	1			T2	4		T10	1		T12	9
valid_sources[0x54]	269008	1			T2	6		T11	3		T24	8
valid_sources[0x55]	252624	1			T2	1		T6	2		T10	8
valid_sources[0x56]	312157	1			T2	6		T5	10		T6	1
valid_sources[0x57]	250165	1			T2	3		T10	4		T24	8
valid_sources[0x58]	325308	1			T2	3		T6	1		T10	1
valid_sources[0x59]	241968	1			T2	2		T6	4		T11	1
valid_sources[0x5a]	260612	1			T2	11		T5	18		T11	7
valid_sources[0x5b]	239315	1			T2	6		T10	3		T11	2
valid_sources[0x5c]	265933	1			T24	9		T13	42		T21	22
valid_sources[0x5d]	267487	1			T2	4		T6	2		T10	1
valid_sources[0x5e]	346721	1			T2	2		T9	1		T10	2
valid_sources[0x5f]	292896	1			T2	2		T6	2		T11	1
valid_sources[0x60]	331684	1			T2	1		T6	2		T11	2
valid_sources[0x61]	246758	1			T2	1		T10	4		T11	1
valid_sources[0x62]	258829	1			T5	7		T8	1		T10	3
valid_sources[0x63]	306401	1			T2	2		T11	1		T12	8
valid_sources[0x64]	257173	1			T11	4		T24	9		T13	96
valid_sources[0x65]	288581	1			T2	8		T10	3		T11	4
valid_sources[0x66]	249993	1			T2	4		T11	2		T12	5
valid_sources[0x67]	270266	1			T2	1		T5	14		T9	2
valid_sources[0x68]	250089	1			T2	2		T6	2		T11	3
valid_sources[0x69]	266710	1			T4	1		T6	1		T10	2
valid_sources[0x6a]	256017	1			T2	7		T6	1		T10	1
valid_sources[0x6b]	308420	1			T2	1		T6	1		T8	1
valid_sources[0x6c]	249925	1			T2	1		T4	1		T6	1
valid_sources[0x6d]	306277	1			T2	2		T5	2		T9	1
valid_sources[0x6e]	282597	1			T2	9		T10	8		T11	1
valid_sources[0x6f]	283681	1			T2	4		T6	1		T24	6
valid_sources[0x70]	244453	1			T2	1		T10	1		T12	12
valid_sources[0x71]	262163	1			T2	3		T4	1		T10	5
valid_sources[0x72]	252236	1			T2	4		T5	4		T6	1
valid_sources[0x73]	256086	1			T2	4		T6	1		T10	7
valid_sources[0x74]	278128	1			T2	1		T6	3		T10	4
valid_sources[0x75]	257108	1			T2	3		T11	2		T24	9
valid_sources[0x76]	334070	1			T2	1		T6	1		T9	1
valid_sources[0x77]	290346	1			T2	3		T6	2		T11	3
valid_sources[0x78]	265610	1			T2	6		T5	13		T8	1
valid_sources[0x79]	261783	1			T2	4		T5	3		T6	1
valid_sources[0x7a]	327558	1			T2	6		T11	1		T12	34
valid_sources[0x7b]	248329	1			T2	14		T6	1		T9	1
valid_sources[0x7c]	233626	1			T2	2		T10	4		T11	1
valid_sources[0x7d]	270434	1			T2	7		T10	1		T11	4
valid_sources[0x7e]	268299	1			T6	1		T10	4		T11	1
valid_sources[0x7f]	286216	1			T8	1		T10	1		T11	3
valid_sources[0x80]	297417	1			T2	2		T5	3		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

12440103

1

T1

8

T2

6

T3

1

values[0x0]

all_enables

biggest_size

399764

1

T1

3

T2

8

T5

4

values[0x1]

all_enables

biggest_size

354009

1

T1

2

T2

7

T5

2