Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/uart-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	949431	0	0
ctrl_rd_A	2147483647	25911	0	0
intr_enable_rd_A	2147483647	24560	0	0
ovrd_rd_A	2147483647	24106	0	0
timeout_ctrl_rd_A	2147483647	24046	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	949431	0	0
T13	268787	7446	0	0
T15	174197	0	0	0
T16	289925	0	0	0
T17	263306	0	0	0
T18	171307	0	0	0
T19	409437	0	0	0
T21	71643	0	0	0
T27	0	5110	0	0
T28	0	10876	0	0
T30	909	0	0	0
T33	0	4624	0	0
T34	0	11743	0	0
T35	0	4806	0	0
T36	0	8828	0	0
T37	0	10341	0	0
T38	0	6506	0	0
T39	0	10770	0	0
T40	26463	0	0	0
T41	680560	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	25911	0	0
T13	268787	895	0	0
T15	174197	0	0	0
T16	289925	0	0	0
T17	263306	0	0	0
T18	171307	0	0	0
T19	409437	0	0	0
T21	71643	0	0	0
T30	909	0	0	0
T35	0	580	0	0
T37	0	584	0	0
T40	26463	0	0	0
T41	680560	0	0	0
T86	0	402	0	0
T87	0	385	0	0
T88	0	219	0	0
T89	0	554	0	0
T90	0	301	0	0
T91	0	348	0	0
T92	0	606	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	24560	0	0
T13	268787	586	0	0
T15	174197	0	0	0
T16	289925	0	0	0
T17	263306	0	0	0
T18	171307	0	0	0
T19	409437	0	0	0
T21	71643	0	0	0
T30	909	0	0	0
T35	0	534	0	0
T37	0	513	0	0
T40	26463	0	0	0
T41	680560	0	0	0
T86	0	384	0	0
T87	0	416	0	0
T88	0	281	0	0
T89	0	557	0	0
T90	0	325	0	0
T91	0	196	0	0
T93	0	26	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	24106	0	0
T13	268787	754	0	0
T15	174197	0	0	0
T16	289925	0	0	0
T17	263306	0	0	0
T18	171307	0	0	0
T19	409437	0	0	0
T21	71643	0	0	0
T30	909	0	0	0
T35	0	514	0	0
T37	0	508	0	0
T40	26463	0	0	0
T41	680560	0	0	0
T86	0	309	0	0
T87	0	418	0	0
T88	0	302	0	0
T89	0	525	0	0
T90	0	265	0	0
T91	0	361	0	0
T92	0	615	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	24046	0	0
T13	268787	784	0	0
T15	174197	0	0	0
T16	289925	0	0	0
T17	263306	0	0	0
T18	171307	0	0	0
T19	409437	0	0	0
T21	71643	0	0	0
T30	909	0	0	0
T35	0	584	0	0
T37	0	508	0	0
T40	26463	0	0	0
T41	680560	0	0	0
T86	0	327	0	0
T87	0	406	0	0
T88	0	344	0	0
T89	0	661	0	0
T90	0	324	0	0
T91	0	270	0	0
T92	0	716	0	0