Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	61914601	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

13168465

1

T1

10

T2

10

T3

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	73918469	1			T1	2069		T2	32		T3	650
values[0x0]	565553	1			T1	5		T2	6		T3	26
values[0x1]	599044	1			T1	8		T2	7		T3	28

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42705240	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

32377826

1

T1

723

T2

20

T3

242

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	312170	1			T1	9		T3	5		T4	11
valid_sources[0x01]	276359	1			T1	7		T3	3		T4	9
valid_sources[0x02]	281908	1			T1	9		T3	1		T4	18
valid_sources[0x03]	288920	1			T1	4		T3	2		T4	8
valid_sources[0x04]	279908	1			T1	7		T3	5		T4	8
valid_sources[0x05]	275547	1			T1	5		T3	3		T4	18
valid_sources[0x06]	263868	1			T1	2		T3	1		T4	12
valid_sources[0x07]	437659	1			T1	7		T3	4		T4	14
valid_sources[0x08]	294059	1			T1	6		T3	4		T4	10
valid_sources[0x09]	264286	1			T1	9		T3	3		T4	9
valid_sources[0x0a]	299981	1			T1	5		T3	3		T4	9
valid_sources[0x0b]	335258	1			T1	9		T3	1		T4	8
valid_sources[0x0c]	284558	1			T1	10		T3	4		T4	7
valid_sources[0x0d]	286178	1			T1	12		T3	1		T4	6
valid_sources[0x0e]	263746	1			T1	13		T3	2		T4	9
valid_sources[0x0f]	276513	1			T1	9		T3	3		T4	13
valid_sources[0x10]	280112	1			T1	7		T4	8		T7	42
valid_sources[0x11]	270543	1			T1	11		T3	4		T4	5
valid_sources[0x12]	344501	1			T1	11		T3	8		T4	3
valid_sources[0x13]	285299	1			T1	5		T3	3		T4	6
valid_sources[0x14]	272337	1			T1	6		T3	2		T4	11
valid_sources[0x15]	306637	1			T1	9		T3	3		T4	5
valid_sources[0x16]	278142	1			T1	8		T3	4		T4	15
valid_sources[0x17]	296103	1			T1	5		T3	4		T4	10
valid_sources[0x18]	311484	1			T1	7		T3	6		T4	9
valid_sources[0x19]	262308	1			T1	19		T3	2		T4	7
valid_sources[0x1a]	326338	1			T1	13		T3	2		T4	6
valid_sources[0x1b]	275467	1			T1	10		T3	6		T4	9
valid_sources[0x1c]	308344	1			T1	14		T3	3		T4	4
valid_sources[0x1d]	284867	1			T1	3		T3	4		T4	6
valid_sources[0x1e]	275750	1			T1	5		T3	4		T4	11
valid_sources[0x1f]	412671	1			T1	6		T3	1		T4	9
valid_sources[0x20]	262468	1			T1	4		T3	5		T4	8
valid_sources[0x21]	278061	1			T1	6		T3	2		T4	13
valid_sources[0x22]	276232	1			T1	8		T3	5		T4	10
valid_sources[0x23]	273085	1			T1	7		T3	1		T4	11
valid_sources[0x24]	408064	1			T1	9		T3	4		T4	10
valid_sources[0x25]	270612	1			T1	7		T3	3		T4	5
valid_sources[0x26]	280701	1			T1	6		T3	2		T4	14
valid_sources[0x27]	295700	1			T1	10		T3	1		T4	9
valid_sources[0x28]	302752	1			T1	8		T3	5		T4	4
valid_sources[0x29]	345769	1			T1	3		T3	3		T4	13
valid_sources[0x2a]	284702	1			T1	7		T3	1		T4	10
valid_sources[0x2b]	276446	1			T1	9		T3	5		T4	13
valid_sources[0x2c]	336795	1			T1	15		T3	3		T4	9
valid_sources[0x2d]	281506	1			T1	9		T3	2		T4	9
valid_sources[0x2e]	296574	1			T1	12		T4	9		T7	34
valid_sources[0x2f]	281475	1			T1	7		T3	3		T4	13
valid_sources[0x30]	314482	1			T1	8		T3	3		T4	9
valid_sources[0x31]	270670	1			T1	12		T3	3		T4	14
valid_sources[0x32]	281066	1			T1	7		T3	2		T4	9
valid_sources[0x33]	264408	1			T1	6		T3	1		T4	8
valid_sources[0x34]	285793	1			T1	13		T3	2		T4	13
valid_sources[0x35]	312855	1			T1	10		T3	2		T4	6
valid_sources[0x36]	283900	1			T1	8		T3	2		T4	14
valid_sources[0x37]	279011	1			T1	10		T3	3		T4	5
valid_sources[0x38]	274731	1			T1	8		T3	3		T4	7
valid_sources[0x39]	274574	1			T1	6		T3	5		T4	10
valid_sources[0x3a]	268404	1			T1	17		T3	1		T4	4
valid_sources[0x3b]	284180	1			T1	11		T4	14		T7	35
valid_sources[0x3c]	271342	1			T1	15		T3	3		T4	8
valid_sources[0x3d]	259853	1			T1	4		T3	2		T4	10
valid_sources[0x3e]	298768	1			T1	6		T3	3		T4	7
valid_sources[0x3f]	327623	1			T1	5		T3	1		T4	7
valid_sources[0x40]	358274	1			T1	9		T3	1		T4	15
valid_sources[0x41]	298252	1			T1	9		T3	5		T4	7
valid_sources[0x42]	265410	1			T1	9		T3	4		T4	6
valid_sources[0x43]	282473	1			T1	11		T3	3		T4	6
valid_sources[0x44]	292122	1			T1	1		T3	4		T4	7
valid_sources[0x45]	323575	1			T1	10		T3	2		T4	10
valid_sources[0x46]	272516	1			T1	5		T3	2		T4	16
valid_sources[0x47]	309932	1			T1	2		T3	1		T4	8
valid_sources[0x48]	271391	1			T1	7		T3	2		T4	10
valid_sources[0x49]	300823	1			T1	17		T3	1		T4	6
valid_sources[0x4a]	393165	1			T1	5		T3	2		T4	4
valid_sources[0x4b]	282140	1			T1	9		T3	2		T4	15
valid_sources[0x4c]	284780	1			T1	10		T3	1		T4	6
valid_sources[0x4d]	359355	1			T1	10		T3	4		T4	7
valid_sources[0x4e]	267084	1			T1	14		T3	4		T4	5
valid_sources[0x4f]	271706	1			T1	16		T4	5		T7	34
valid_sources[0x50]	283853	1			T1	7		T3	4		T4	8
valid_sources[0x51]	280565	1			T1	6		T3	9		T4	7
valid_sources[0x52]	301921	1			T1	13		T3	2		T4	8
valid_sources[0x53]	260579	1			T1	10		T4	10		T7	50
valid_sources[0x54]	268259	1			T1	9		T3	1		T4	9
valid_sources[0x55]	268599	1			T1	8		T3	4		T4	10
valid_sources[0x56]	300673	1			T1	9		T3	5		T4	8
valid_sources[0x57]	353616	1			T1	5		T3	1		T4	5
valid_sources[0x58]	290597	1			T1	2		T3	3		T4	8
valid_sources[0x59]	265323	1			T1	10		T3	5		T4	10
valid_sources[0x5a]	279117	1			T1	5		T3	1		T4	3
valid_sources[0x5b]	272179	1			T1	11		T3	1		T4	3
valid_sources[0x5c]	257674	1			T1	14		T3	4		T4	13
valid_sources[0x5d]	307039	1			T1	15		T3	1		T4	9
valid_sources[0x5e]	275079	1			T1	13		T3	2		T4	9
valid_sources[0x5f]	306769	1			T1	6		T3	1		T4	11
valid_sources[0x60]	294233	1			T1	9		T3	4		T4	8
valid_sources[0x61]	286564	1			T1	9		T3	3		T4	9
valid_sources[0x62]	309140	1			T1	6		T3	4		T4	15
valid_sources[0x63]	311079	1			T1	11		T3	2		T4	10
valid_sources[0x64]	287760	1			T1	5		T3	4		T4	12
valid_sources[0x65]	281606	1			T1	13		T4	11		T7	38
valid_sources[0x66]	272456	1			T1	6		T3	3		T4	8
valid_sources[0x67]	264709	1			T1	18		T3	2		T4	4
valid_sources[0x68]	276491	1			T1	15		T3	1		T4	11
valid_sources[0x69]	287730	1			T1	5		T3	2		T4	14
valid_sources[0x6a]	274657	1			T1	6		T3	4		T4	14
valid_sources[0x6b]	273092	1			T1	3		T4	5		T7	41
valid_sources[0x6c]	272963	1			T1	14		T3	5		T4	9
valid_sources[0x6d]	271276	1			T1	5		T3	2		T4	14
valid_sources[0x6e]	273729	1			T1	7		T3	4		T4	12
valid_sources[0x6f]	275493	1			T1	14		T3	2		T4	8
valid_sources[0x70]	266409	1			T1	9		T3	2		T4	13
valid_sources[0x71]	379700	1			T1	11		T3	4		T4	6
valid_sources[0x72]	280367	1			T1	16		T3	4		T4	8
valid_sources[0x73]	272390	1			T1	1		T3	5		T4	6
valid_sources[0x74]	257241	1			T1	5		T3	3		T4	9
valid_sources[0x75]	264382	1			T1	12		T4	11		T7	36
valid_sources[0x76]	266956	1			T1	6		T3	8		T4	4
valid_sources[0x77]	266671	1			T1	8		T3	4		T4	8
valid_sources[0x78]	283129	1			T1	3		T3	5		T4	13
valid_sources[0x79]	335808	1			T1	5		T3	1		T4	4
valid_sources[0x7a]	314096	1			T1	6		T3	7		T4	9
valid_sources[0x7b]	278980	1			T1	13		T3	6		T4	10
valid_sources[0x7c]	347734	1			T1	8		T3	2		T4	6
valid_sources[0x7d]	278627	1			T1	4		T3	4		T4	14
valid_sources[0x7e]	296100	1			T1	7		T3	3		T4	6
valid_sources[0x7f]	380911	1			T1	7		T3	2		T4	12
valid_sources[0x80]	393318	1			T1	11		T3	3		T4	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

12441929

1

T1

4

T2

7

T3

8

values[0x0]

all_enables

biggest_size

387540

1

T1

2

T2

1

T3

10

values[0x1]

all_enables

biggest_size

338996

1

T1

4

T2

2

T3

4