Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 63059313 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 14334304 1 T1 11 T2 18 T3 28



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x4] 76286403 1 T1 1253 T2 684 T3 103
values[0x0] 538652 1 T1 5 T2 34 T3 16
values[0x1] 568562 1 T1 8 T2 21 T3 14



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 43633785 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 33759832 1 T1 426 T2 254 T3 69



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
valid_sources[0x00] 293128 1 T1 14 T8 65 T9 58
valid_sources[0x01] 332341 1 T1 2 T8 51 T9 54
valid_sources[0x02] 280281 1 T1 9 T3 1 T7 1
valid_sources[0x03] 275763 1 T1 10 T8 54 T9 39
valid_sources[0x04] 285493 1 T2 9 T7 1 T8 67
valid_sources[0x05] 288959 1 T1 8 T8 49 T9 55
valid_sources[0x06] 293528 1 T3 1 T5 1 T8 57
valid_sources[0x07] 290360 1 T1 2 T8 74 T9 43
valid_sources[0x08] 310467 1 T8 62 T9 54 T11 19
valid_sources[0x09] 292837 1 T8 45 T9 67 T11 30
valid_sources[0x0a] 308631 1 T1 8 T8 46 T9 56
valid_sources[0x0b] 284358 1 T1 1 T8 51 T9 43
valid_sources[0x0c] 282331 1 T8 60 T9 56 T11 38
valid_sources[0x0d] 290736 1 T8 50 T9 45 T11 24
valid_sources[0x0e] 287756 1 T7 1 T8 66 T9 66
valid_sources[0x0f] 325552 1 T1 1 T5 1 T8 68
valid_sources[0x10] 283758 1 T1 8 T8 74 T9 46
valid_sources[0x11] 318096 1 T1 12 T8 47 T9 46
valid_sources[0x12] 292166 1 T1 3 T8 50 T9 58
valid_sources[0x13] 289603 1 T8 48 T9 27 T11 25
valid_sources[0x14] 261913 1 T1 10 T7 3 T8 58
valid_sources[0x15] 288527 1 T1 3 T8 68 T9 51
valid_sources[0x16] 297414 1 T1 5 T2 36 T3 2
valid_sources[0x17] 298022 1 T1 9 T8 64 T9 47
valid_sources[0x18] 396509 1 T1 17 T8 61 T9 38
valid_sources[0x19] 289192 1 T1 6 T8 45 T9 49
valid_sources[0x1a] 292381 1 T1 3 T8 52 T9 46
valid_sources[0x1b] 299601 1 T8 52 T9 51 T11 33
valid_sources[0x1c] 347898 1 T5 4 T8 76 T9 56
valid_sources[0x1d] 300501 1 T1 4 T7 1 T8 59
valid_sources[0x1e] 286723 1 T1 2 T7 1 T8 59
valid_sources[0x1f] 272141 1 T1 14 T3 3 T8 54
valid_sources[0x20] 273019 1 T8 67 T9 60 T11 32
valid_sources[0x21] 291106 1 T1 14 T3 1 T8 58
valid_sources[0x22] 293337 1 T1 21 T8 52 T9 39
valid_sources[0x23] 307603 1 T1 19 T3 1 T8 61
valid_sources[0x24] 280039 1 T1 2 T8 50 T9 53
valid_sources[0x25] 305123 1 T1 1 T8 58 T9 39
valid_sources[0x26] 282902 1 T1 1 T3 1 T8 55
valid_sources[0x27] 302707 1 T3 2 T8 64 T9 53
valid_sources[0x28] 276635 1 T1 6 T3 1 T8 72
valid_sources[0x29] 302504 1 T1 1 T8 54 T9 47
valid_sources[0x2a] 280220 1 T1 1 T8 40 T9 47
valid_sources[0x2b] 300946 1 T1 5 T8 59 T9 48
valid_sources[0x2c] 318040 1 T1 1 T8 63 T9 46
valid_sources[0x2d] 288216 1 T1 1 T3 2 T8 56
valid_sources[0x2e] 348265 1 T1 5 T8 65 T9 39
valid_sources[0x2f] 320969 1 T8 62 T9 53 T11 38
valid_sources[0x30] 264712 1 T1 7 T3 1 T8 57
valid_sources[0x31] 292196 1 T1 7 T3 6 T8 73
valid_sources[0x32] 282626 1 T1 3 T8 63 T9 39
valid_sources[0x33] 322423 1 T3 2 T8 67 T9 48
valid_sources[0x34] 267961 1 T1 1 T8 57 T9 44
valid_sources[0x35] 272337 1 T1 7 T3 6 T8 55
valid_sources[0x36] 277543 1 T1 5 T3 2 T8 55
valid_sources[0x37] 263303 1 T8 68 T9 39 T11 40
valid_sources[0x38] 490148 1 T1 2 T7 1 T8 49
valid_sources[0x39] 264153 1 T8 63 T9 42 T11 39
valid_sources[0x3a] 308605 1 T1 8 T3 1 T8 53
valid_sources[0x3b] 323336 1 T1 9 T2 22 T3 2
valid_sources[0x3c] 298103 1 T1 6 T3 1 T4 1
valid_sources[0x3d] 324344 1 T1 5 T8 63 T9 50
valid_sources[0x3e] 286610 1 T1 2 T8 66 T9 40
valid_sources[0x3f] 292185 1 T8 58 T9 36 T11 45
valid_sources[0x40] 289622 1 T1 3 T8 72 T9 41
valid_sources[0x41] 308470 1 T8 61 T9 54 T11 27
valid_sources[0x42] 343157 1 T1 8 T8 56 T9 38
valid_sources[0x43] 257252 1 T1 4 T8 48 T9 45
valid_sources[0x44] 291419 1 T1 14 T7 1 T8 62
valid_sources[0x45] 294368 1 T8 68 T9 47 T11 33
valid_sources[0x46] 289111 1 T8 55 T9 43 T11 32
valid_sources[0x47] 327221 1 T8 59 T9 47 T11 34
valid_sources[0x48] 301355 1 T3 3 T8 56 T9 49
valid_sources[0x49] 314094 1 T1 8 T7 1 T8 54
valid_sources[0x4a] 276241 1 T1 5 T8 62 T9 44
valid_sources[0x4b] 316322 1 T1 4 T8 55 T9 51
valid_sources[0x4c] 279821 1 T1 1 T3 1 T8 70
valid_sources[0x4d] 353222 1 T2 29 T8 65 T9 49
valid_sources[0x4e] 274702 1 T1 2 T3 1 T8 54
valid_sources[0x4f] 311882 1 T1 23 T2 11 T8 56
valid_sources[0x50] 299848 1 T1 4 T8 71 T9 50
valid_sources[0x51] 293031 1 T1 8 T8 47 T9 42
valid_sources[0x52] 279125 1 T8 56 T9 48 T11 29
valid_sources[0x53] 267170 1 T1 12 T3 2 T7 1
valid_sources[0x54] 279311 1 T1 10 T2 32 T3 2
valid_sources[0x55] 279973 1 T1 8 T5 1 T8 64
valid_sources[0x56] 281399 1 T1 3 T8 59 T9 42
valid_sources[0x57] 290172 1 T1 6 T8 59 T9 49
valid_sources[0x58] 279297 1 T1 8 T8 62 T9 51
valid_sources[0x59] 263385 1 T1 6 T8 53 T9 45
valid_sources[0x5a] 473643 1 T5 1 T8 57 T9 60
valid_sources[0x5b] 312162 1 T1 1 T8 59 T9 45
valid_sources[0x5c] 307287 1 T1 5 T7 1 T8 59
valid_sources[0x5d] 279688 1 T1 10 T8 64 T9 66
valid_sources[0x5e] 263149 1 T1 4 T3 2 T8 51
valid_sources[0x5f] 319394 1 T1 10 T5 1 T8 60
valid_sources[0x60] 320420 1 T8 48 T9 43 T11 27
valid_sources[0x61] 418377 1 T1 9 T5 1 T7 1
valid_sources[0x62] 341964 1 T1 9 T8 54 T9 46
valid_sources[0x63] 260969 1 T1 6 T8 61 T9 45
valid_sources[0x64] 293081 1 T1 2 T5 1 T8 66
valid_sources[0x65] 293099 1 T1 9 T3 1 T8 50
valid_sources[0x66] 260529 1 T1 1 T3 2 T8 76
valid_sources[0x67] 342563 1 T1 8 T8 59 T9 35
valid_sources[0x68] 293383 1 T8 63 T9 48 T11 38
valid_sources[0x69] 278407 1 T2 5 T3 2 T5 1
valid_sources[0x6a] 276632 1 T1 6 T7 3 T8 43
valid_sources[0x6b] 322153 1 T1 2 T7 2 T8 71
valid_sources[0x6c] 310946 1 T5 1 T8 64 T9 31
valid_sources[0x6d] 357855 1 T1 4 T8 67 T9 41
valid_sources[0x6e] 335692 1 T3 3 T8 63 T9 47
valid_sources[0x6f] 283017 1 T3 5 T8 52 T9 40
valid_sources[0x70] 288155 1 T1 5 T8 56 T9 52
valid_sources[0x71] 281837 1 T1 3 T8 62 T9 55
valid_sources[0x72] 309017 1 T1 3 T7 1 T8 50
valid_sources[0x73] 275500 1 T1 8 T3 1 T8 53
valid_sources[0x74] 258275 1 T2 12 T3 2 T8 49
valid_sources[0x75] 344325 1 T1 4 T8 63 T9 60
valid_sources[0x76] 295383 1 T3 1 T8 60 T9 57
valid_sources[0x77] 279263 1 T1 14 T8 58 T9 48
valid_sources[0x78] 349044 1 T1 2 T8 51 T9 43
valid_sources[0x79] 320723 1 T1 6 T7 2 T8 56
valid_sources[0x7a] 287707 1 T8 54 T9 42 T11 33
valid_sources[0x7b] 369271 1 T1 3 T8 66 T9 40
valid_sources[0x7c] 270270 1 T8 60 T9 46 T11 29
valid_sources[0x7d] 270876 1 T1 4 T5 2 T8 73
valid_sources[0x7e] 309905 1 T1 7 T8 66 T9 43
valid_sources[0x7f] 356711 1 T1 3 T3 3 T5 4
valid_sources[0x80] 298434 1 T1 20 T8 62 T9 63



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcode   cp_mask   cp_size   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x4] all_enables biggest_size 13637232 1 T1 4 T2 5 T3 4
values[0x0] all_enables biggest_size 372115 1 T1 4 T2 9 T3 12
values[0x1] all_enables biggest_size 324957 1 T1 3 T2 4 T3 12