Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/uart-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	851684	0	0
ctrl_rd_A	2147483647	24738	0	0
intr_enable_rd_A	2147483647	23270	0	0
ovrd_rd_A	2147483647	22619	0	0
timeout_ctrl_rd_A	2147483647	22191	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	851684	0	0
T9	272701	6770	0	0
T10	541769	0	0	0
T11	812625	0	0	0
T12	275692	0	0	0
T14	77587	0	0	0
T15	46107	0	0	0
T16	891442	0	0	0
T20	0	3576	0	0
T21	68474	1670	0	0
T29	3192	0	0	0
T30	1381	0	0	0
T33	0	2484	0	0
T34	0	18530	0	0
T35	0	7656	0	0
T36	0	5796	0	0
T37	0	6859	0	0
T38	0	15281	0	0
T39	0	5330	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	24738	0	0
T9	272701	645	0	0
T10	541769	0	0	0
T11	812625	0	0	0
T12	275692	0	0	0
T14	77587	0	0	0
T15	46107	0	0	0
T16	891442	0	0	0
T20	0	408	0	0
T21	68474	254	0	0
T29	3192	0	0	0
T30	1381	0	0	0
T33	0	230	0	0
T35	0	1005	0	0
T36	0	358	0	0
T39	0	680	0	0
T83	0	339	0	0
T84	0	361	0	0
T85	0	640	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	23270	0	0
T9	272701	782	0	0
T10	541769	0	0	0
T11	812625	0	0	0
T12	275692	0	0	0
T14	77587	0	0	0
T15	46107	0	0	0
T16	891442	0	0	0
T20	0	371	0	0
T21	68474	204	0	0
T29	3192	0	0	0
T30	1381	0	0	0
T33	0	164	0	0
T35	0	886	0	0
T36	0	257	0	0
T39	0	566	0	0
T83	0	299	0	0
T84	0	388	0	0
T85	0	528	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22619	0	0
T9	272701	773	0	0
T10	541769	0	0	0
T11	812625	0	0	0
T12	275692	0	0	0
T14	77587	0	0	0
T15	46107	0	0	0
T16	891442	0	0	0
T20	0	350	0	0
T21	68474	194	0	0
T29	3192	0	0	0
T30	1381	0	0	0
T33	0	206	0	0
T35	0	965	0	0
T36	0	309	0	0
T39	0	539	0	0
T83	0	390	0	0
T84	0	437	0	0
T85	0	549	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22191	0	0
T9	272701	749	0	0
T10	541769	0	0	0
T11	812625	0	0	0
T12	275692	0	0	0
T14	77587	0	0	0
T15	46107	0	0	0
T16	891442	0	0	0
T20	0	292	0	0
T21	68474	251	0	0
T29	3192	0	0	0
T30	1381	0	0	0
T33	0	216	0	0
T35	0	1069	0	0
T36	0	307	0	0
T39	0	479	0	0
T83	0	340	0	0
T84	0	370	0	0
T85	0	517	0	0