Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	59890540	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

13194837

1

T1

6

T2

1

T3

16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	71919727	1			T1	1		T2	1		T3	1506
values[0x0]	565964	1			T1	5		T3	20		T4	8
values[0x1]	599686	1			T1	8		T3	29		T4	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41316403	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

31768974

1

T1

7

T2

1

T3

521

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	249751	1			T3	1		T5	1		T8	2
valid_sources[0x01]	267134	1			T3	9		T4	1		T5	17
valid_sources[0x02]	408238	1			T3	15		T4	2		T5	9
valid_sources[0x03]	294009	1			T3	5		T4	2		T5	3
valid_sources[0x04]	245579	1			T3	2		T5	9		T8	9
valid_sources[0x05]	290351	1			T3	13		T5	16		T8	2
valid_sources[0x06]	281641	1			T5	10		T8	4		T10	1
valid_sources[0x07]	325468	1			T3	8		T5	7		T8	7
valid_sources[0x08]	293404	1			T3	4		T5	6		T6	1
valid_sources[0x09]	290164	1			T3	9		T5	2		T8	6
valid_sources[0x0a]	253905	1			T3	5		T5	3		T8	2
valid_sources[0x0b]	259042	1			T5	6		T8	2		T10	2
valid_sources[0x0c]	280873	1			T3	2		T5	17		T8	12
valid_sources[0x0d]	248762	1			T3	3		T8	7		T10	3
valid_sources[0x0e]	364964	1			T3	4		T5	9		T7	1
valid_sources[0x0f]	244993	1			T3	1		T4	1		T8	10
valid_sources[0x10]	256635	1			T3	3		T5	30		T8	3
valid_sources[0x11]	269851	1			T3	10		T5	2		T8	3
valid_sources[0x12]	275591	1			T3	11		T5	3		T8	8
valid_sources[0x13]	265870	1			T3	6		T5	9		T8	2
valid_sources[0x14]	269977	1			T3	6		T5	5		T8	12
valid_sources[0x15]	271296	1			T3	4		T4	1		T8	2
valid_sources[0x16]	280081	1			T3	8		T5	7		T8	2
valid_sources[0x17]	317633	1			T3	14		T4	1		T5	2
valid_sources[0x18]	256788	1			T3	9		T5	7		T8	5
valid_sources[0x19]	333526	1			T3	2		T5	1		T8	2
valid_sources[0x1a]	316418	1			T3	4		T5	8		T8	2
valid_sources[0x1b]	336857	1			T3	10		T5	9		T8	2
valid_sources[0x1c]	262952	1			T3	9		T5	2		T8	7
valid_sources[0x1d]	327767	1			T3	9		T5	8		T8	3
valid_sources[0x1e]	257718	1			T3	9		T4	1		T5	4
valid_sources[0x1f]	276313	1			T3	10		T5	6		T8	5
valid_sources[0x20]	249462	1			T3	6		T5	17		T8	6
valid_sources[0x21]	284054	1			T3	2		T4	1		T5	4
valid_sources[0x22]	285122	1			T3	5		T5	4		T8	6
valid_sources[0x23]	258044	1			T3	3		T4	1		T5	1
valid_sources[0x24]	293880	1			T3	9		T4	1		T5	3
valid_sources[0x25]	270793	1			T3	6		T5	9		T8	6
valid_sources[0x26]	248692	1			T3	8		T5	7		T8	5
valid_sources[0x27]	249512	1			T3	6		T5	7		T8	4
valid_sources[0x28]	252771	1			T3	3		T5	3		T8	4
valid_sources[0x29]	280344	1			T3	7		T5	9		T8	6
valid_sources[0x2a]	391321	1			T3	5		T5	20		T8	7
valid_sources[0x2b]	291895	1			T3	4		T5	1		T8	5
valid_sources[0x2c]	281427	1			T3	3		T5	1		T8	15
valid_sources[0x2d]	320733	1			T3	11		T8	3		T10	5
valid_sources[0x2e]	247667	1			T3	6		T5	7		T8	3
valid_sources[0x2f]	245906	1			T3	1		T5	5		T8	3
valid_sources[0x30]	269790	1			T3	10		T5	19		T8	13
valid_sources[0x31]	273114	1			T3	12		T5	2		T8	2
valid_sources[0x32]	248698	1			T3	13		T5	2		T8	6
valid_sources[0x33]	255638	1			T3	5		T5	2		T8	9
valid_sources[0x34]	264862	1			T3	8		T5	10		T8	5
valid_sources[0x35]	293816	1			T3	11		T4	1		T5	5
valid_sources[0x36]	271549	1			T3	7		T5	1		T8	8
valid_sources[0x37]	284644	1			T3	2		T8	4		T10	10
valid_sources[0x38]	267138	1			T3	4		T5	15		T10	7
valid_sources[0x39]	272190	1			T3	4		T5	9		T6	1
valid_sources[0x3a]	277401	1			T3	6		T5	6		T6	1
valid_sources[0x3b]	467707	1			T3	3		T5	6		T8	3
valid_sources[0x3c]	264551	1			T3	6		T5	2		T8	4
valid_sources[0x3d]	355048	1			T3	2		T8	1		T10	3
valid_sources[0x3e]	384931	1			T3	3		T4	1		T5	8
valid_sources[0x3f]	295764	1			T3	3		T5	9		T8	5
valid_sources[0x40]	272913	1			T3	6		T8	3		T10	3
valid_sources[0x41]	256219	1			T3	10		T8	2		T10	3
valid_sources[0x42]	593472	1			T3	4		T4	1		T8	8
valid_sources[0x43]	384606	1			T3	6		T5	5		T8	6
valid_sources[0x44]	296574	1			T2	1		T3	4		T5	2
valid_sources[0x45]	265084	1			T3	5		T5	6		T6	1
valid_sources[0x46]	285906	1			T3	13		T4	1		T5	3
valid_sources[0x47]	252160	1			T3	5		T8	4		T10	3
valid_sources[0x48]	256230	1			T3	5		T5	2		T8	8
valid_sources[0x49]	293498	1			T3	5		T6	1		T8	4
valid_sources[0x4a]	281801	1			T3	6		T4	1		T5	1
valid_sources[0x4b]	254989	1			T3	8		T5	16		T8	2
valid_sources[0x4c]	265321	1			T3	3		T5	4		T8	9
valid_sources[0x4d]	293665	1			T3	1		T5	1		T6	1
valid_sources[0x4e]	329071	1			T3	5		T5	14		T8	12
valid_sources[0x4f]	267639	1			T3	7		T8	8		T10	3
valid_sources[0x50]	279465	1			T3	9		T5	4		T6	1
valid_sources[0x51]	249251	1			T3	2		T5	15		T8	1
valid_sources[0x52]	365907	1			T3	3		T5	4		T8	4
valid_sources[0x53]	253237	1			T3	9		T5	4		T6	1
valid_sources[0x54]	279086	1			T3	5		T5	7		T8	4
valid_sources[0x55]	292277	1			T5	1		T8	8		T10	5
valid_sources[0x56]	247916	1			T3	5		T5	4		T8	4
valid_sources[0x57]	343490	1			T3	6		T5	2		T8	2
valid_sources[0x58]	268896	1			T3	7		T8	6		T10	3
valid_sources[0x59]	252142	1			T3	2		T5	8		T8	4
valid_sources[0x5a]	261206	1			T3	7		T4	1		T5	5
valid_sources[0x5b]	308156	1			T3	6		T6	1		T8	7
valid_sources[0x5c]	407848	1			T3	5		T5	4		T8	5
valid_sources[0x5d]	245021	1			T3	6		T4	1		T5	4
valid_sources[0x5e]	267928	1			T3	4		T5	5		T8	5
valid_sources[0x5f]	262720	1			T3	3		T5	3		T10	2
valid_sources[0x60]	262101	1			T3	8		T5	15		T8	5
valid_sources[0x61]	269768	1			T3	9		T5	10		T8	8
valid_sources[0x62]	257879	1			T3	10		T5	4		T8	4
valid_sources[0x63]	310087	1			T3	10		T5	14		T8	7
valid_sources[0x64]	304657	1			T3	4		T5	4		T8	5
valid_sources[0x65]	247982	1			T3	2		T5	12		T8	8
valid_sources[0x66]	310860	1			T3	9		T5	1		T8	8
valid_sources[0x67]	268193	1			T3	3		T5	15		T8	10
valid_sources[0x68]	326813	1			T3	7		T5	2		T8	7
valid_sources[0x69]	249664	1			T3	10		T10	2		T11	11
valid_sources[0x6a]	265481	1			T3	9		T8	3		T10	3
valid_sources[0x6b]	269808	1			T3	8		T5	7		T8	5
valid_sources[0x6c]	283546	1			T3	12		T5	9		T8	8
valid_sources[0x6d]	287224	1			T3	7		T8	1		T10	6
valid_sources[0x6e]	273948	1			T3	4		T5	5		T8	1
valid_sources[0x6f]	306133	1			T3	7		T5	4		T8	4
valid_sources[0x70]	283358	1			T3	6		T5	3		T8	5
valid_sources[0x71]	290971	1			T3	11		T5	5		T8	5
valid_sources[0x72]	257000	1			T3	13		T4	2		T5	3
valid_sources[0x73]	301443	1			T3	10		T5	3		T8	6
valid_sources[0x74]	343257	1			T3	8		T5	5		T8	2
valid_sources[0x75]	346502	1			T3	1		T5	8		T8	13
valid_sources[0x76]	275104	1			T3	7		T5	11		T8	6
valid_sources[0x77]	263321	1			T3	10		T8	9		T10	3
valid_sources[0x78]	258668	1			T3	4		T5	8		T8	3
valid_sources[0x79]	266433	1			T3	13		T5	3		T8	8
valid_sources[0x7a]	276764	1			T3	6		T5	12		T8	8
valid_sources[0x7b]	249410	1			T3	4		T4	1		T5	1
valid_sources[0x7c]	432509	1			T3	7		T5	2		T8	5
valid_sources[0x7d]	321915	1			T3	5		T5	13		T8	12
valid_sources[0x7e]	281021	1			T3	3		T8	9		T10	3
valid_sources[0x7f]	313574	1			T3	6		T5	5		T8	6
valid_sources[0x80]	298113	1			T3	12		T5	2		T8	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

12449429

1

T2

1

T3

7

T4

3

values[0x0]

all_enables

biggest_size

396793

1

T1

3

T3

4

T4

2

values[0x1]

all_enables

biggest_size

348615

1

T1

3

T3

5

T4

1