Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/uart-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	918704	0	0
ctrl_rd_A	2147483647	25314	0	0
intr_enable_rd_A	2147483647	23964	0	0
ovrd_rd_A	2147483647	23305	0	0
timeout_ctrl_rd_A	2147483647	24347	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	918704	0	0
T11	97980	2939	0	0
T12	100606	0	0	0
T13	0	2126	0	0
T15	46162	0	0	0
T16	56796	0	0	0
T17	325894	0	0	0
T21	0	10290	0	0
T24	550940	0	0	0
T31	0	6419	0	0
T34	974	0	0	0
T35	5904	0	0	0
T36	0	4605	0	0
T37	0	13147	0	0
T38	0	6858	0	0
T39	0	1838	0	0
T40	0	9851	0	0
T41	0	6334	0	0
T42	44982	0	0	0
T43	237856	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	25314	0	0
T11	97980	248	0	0
T12	100606	0	0	0
T15	46162	0	0	0
T16	56796	0	0	0
T17	325894	0	0	0
T21	0	1159	0	0
T24	550940	0	0	0
T31	0	641	0	0
T34	974	0	0	0
T35	5904	0	0	0
T38	0	694	0	0
T39	0	302	0	0
T42	44982	0	0	0
T43	237856	0	0	0
T86	0	1007	0	0
T87	0	126	0	0
T88	0	380	0	0
T89	0	725	0	0
T90	0	483	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	23964	0	0
T11	97980	273	0	0
T12	100606	0	0	0
T15	46162	0	0	0
T16	56796	0	0	0
T17	325894	0	0	0
T21	0	1036	0	0
T24	550940	0	0	0
T31	0	701	0	0
T34	974	0	0	0
T35	5904	0	0	0
T38	0	676	0	0
T39	0	267	0	0
T42	44982	0	0	0
T43	237856	0	0	0
T86	0	1017	0	0
T87	0	128	0	0
T88	0	312	0	0
T89	0	630	0	0
T90	0	487	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	23305	0	0
T11	97980	233	0	0
T12	100606	0	0	0
T15	46162	0	0	0
T16	56796	0	0	0
T17	325894	0	0	0
T21	0	1164	0	0
T24	550940	0	0	0
T31	0	641	0	0
T34	974	0	0	0
T35	5904	0	0	0
T38	0	840	0	0
T39	0	321	0	0
T42	44982	0	0	0
T43	237856	0	0	0
T86	0	1097	0	0
T87	0	110	0	0
T88	0	408	0	0
T89	0	733	0	0
T90	0	496	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	24347	0	0
T11	97980	242	0	0
T12	100606	0	0	0
T15	46162	0	0	0
T16	56796	0	0	0
T17	325894	0	0	0
T21	0	1271	0	0
T24	550940	0	0	0
T31	0	685	0	0
T34	974	0	0	0
T35	5904	0	0	0
T38	0	743	0	0
T39	0	286	0	0
T42	44982	0	0	0
T43	237856	0	0	0
T86	0	973	0	0
T87	0	111	0	0
T88	0	330	0	0
T89	0	857	0	0
T90	0	505	0	0