Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	60888896	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

14076261

1

T1

16

T2

39

T3

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	73743317	1			T1	997		T2	48		T3	16
values[0x0]	591966	1			T1	6		T2	19		T3	18
values[0x1]	629874	1			T1	7		T2	14		T3	10

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42110843	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

32854314

1

T1

344

T2

45

T3

19

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	247847	1			T5	8		T7	1		T11	39
valid_sources[0x01]	324665	1			T2	1		T5	8		T7	2
valid_sources[0x02]	387862	1			T4	1		T5	10		T7	6
valid_sources[0x03]	313607	1			T5	12		T7	10		T11	71
valid_sources[0x04]	299255	1			T2	3		T5	6		T6	1
valid_sources[0x05]	297054	1			T5	8		T7	3		T11	58
valid_sources[0x06]	254856	1			T5	5		T7	1		T12	28
valid_sources[0x07]	284149	1			T5	4		T6	1		T7	5
valid_sources[0x08]	258542	1			T5	11		T11	99		T12	53
valid_sources[0x09]	258052	1			T5	13		T6	3		T7	2
valid_sources[0x0a]	317505	1			T3	2		T5	14		T6	1
valid_sources[0x0b]	274480	1			T2	4		T5	5		T6	4
valid_sources[0x0c]	277665	1			T5	3		T6	3		T7	4
valid_sources[0x0d]	270792	1			T5	9		T7	3		T12	29
valid_sources[0x0e]	272346	1			T5	14		T6	2		T7	5
valid_sources[0x0f]	263111	1			T5	10		T6	2		T7	2
valid_sources[0x10]	272623	1			T5	2		T7	5		T11	6
valid_sources[0x11]	356831	1			T5	12		T6	1		T7	3
valid_sources[0x12]	263019	1			T5	12		T6	2		T7	1
valid_sources[0x13]	309768	1			T5	8		T6	1		T7	4
valid_sources[0x14]	275917	1			T5	10		T6	5		T7	2
valid_sources[0x15]	278751	1			T5	11		T7	2		T11	43
valid_sources[0x16]	245349	1			T5	9		T6	1		T7	2
valid_sources[0x17]	249638	1			T5	10		T6	1		T7	1
valid_sources[0x18]	288785	1			T5	13		T12	75		T22	1
valid_sources[0x19]	303821	1			T5	10		T6	1		T7	1
valid_sources[0x1a]	288946	1			T5	11		T7	1		T12	43
valid_sources[0x1b]	281383	1			T5	13		T11	19		T12	43
valid_sources[0x1c]	261971	1			T2	2		T5	9		T7	2
valid_sources[0x1d]	277170	1			T5	3		T7	1		T11	12
valid_sources[0x1e]	294637	1			T5	8		T11	31		T12	28
valid_sources[0x1f]	279844	1			T5	13		T7	2		T12	46
valid_sources[0x20]	426614	1			T5	2		T6	1		T7	9
valid_sources[0x21]	445480	1			T5	11		T6	3		T7	3
valid_sources[0x22]	281295	1			T5	8		T6	1		T7	2
valid_sources[0x23]	315424	1			T5	13		T6	2		T7	3
valid_sources[0x24]	263088	1			T5	7		T11	34		T12	38
valid_sources[0x25]	416837	1			T5	4		T7	2		T11	45
valid_sources[0x26]	276281	1			T5	9		T6	1		T12	42
valid_sources[0x27]	299302	1			T5	10		T11	7		T12	20
valid_sources[0x28]	347489	1			T2	2		T5	14		T6	2
valid_sources[0x29]	298839	1			T5	11		T6	2		T7	2
valid_sources[0x2a]	284558	1			T5	13		T6	1		T7	4
valid_sources[0x2b]	269220	1			T5	10		T6	1		T7	7
valid_sources[0x2c]	265367	1			T5	12		T7	10		T32	1
valid_sources[0x2d]	277674	1			T5	8		T6	2		T7	4
valid_sources[0x2e]	282346	1			T5	16		T6	1		T7	8
valid_sources[0x2f]	266774	1			T5	4		T6	1		T7	1
valid_sources[0x30]	253659	1			T2	2		T5	10		T7	1
valid_sources[0x31]	270198	1			T5	10		T6	1		T7	6
valid_sources[0x32]	366471	1			T5	14		T7	6		T11	239
valid_sources[0x33]	346376	1			T5	7		T6	3		T7	3
valid_sources[0x34]	257966	1			T5	6		T7	5		T11	103
valid_sources[0x35]	257926	1			T2	1		T5	6		T6	2
valid_sources[0x36]	271109	1			T3	7		T5	20		T11	45
valid_sources[0x37]	275836	1			T5	13		T7	6		T11	9
valid_sources[0x38]	292868	1			T2	1		T5	9		T6	1
valid_sources[0x39]	433160	1			T2	1		T5	8		T7	1
valid_sources[0x3a]	285118	1			T5	4		T7	3		T11	96
valid_sources[0x3b]	259272	1			T5	13		T6	1		T7	4
valid_sources[0x3c]	259125	1			T5	9		T6	4		T7	2
valid_sources[0x3d]	270197	1			T5	9		T12	27		T43	2
valid_sources[0x3e]	288546	1			T5	9		T7	6		T11	9
valid_sources[0x3f]	389351	1			T5	10		T6	1		T7	2
valid_sources[0x40]	273943	1			T5	16		T6	4		T7	4
valid_sources[0x41]	294225	1			T5	8		T7	6		T12	47
valid_sources[0x42]	281530	1			T5	13		T6	2		T7	3
valid_sources[0x43]	284521	1			T5	4		T7	3		T12	15
valid_sources[0x44]	259313	1			T5	6		T6	2		T7	2
valid_sources[0x45]	322200	1			T5	3		T7	3		T15	1257
valid_sources[0x46]	291727	1			T5	7		T6	3		T7	6
valid_sources[0x47]	261570	1			T5	16		T7	2		T12	44
valid_sources[0x48]	306087	1			T5	12		T6	3		T7	2
valid_sources[0x49]	270437	1			T5	15		T7	6		T12	48
valid_sources[0x4a]	265338	1			T2	3		T5	6		T7	1
valid_sources[0x4b]	292541	1			T5	9		T7	8		T9	1
valid_sources[0x4c]	279708	1			T5	11		T11	6		T12	12
valid_sources[0x4d]	264075	1			T2	1		T5	9		T6	3
valid_sources[0x4e]	276353	1			T5	13		T6	1		T7	1
valid_sources[0x4f]	371909	1			T5	11		T6	1		T7	5
valid_sources[0x50]	289954	1			T5	8		T6	1		T7	4
valid_sources[0x51]	254679	1			T5	14		T7	4		T12	34
valid_sources[0x52]	273422	1			T5	10		T7	8		T12	27
valid_sources[0x53]	309214	1			T2	2		T5	7		T6	3
valid_sources[0x54]	278548	1			T5	8		T7	6		T11	32
valid_sources[0x55]	290839	1			T5	10		T12	19		T22	4
valid_sources[0x56]	271865	1			T3	1		T5	7		T7	2
valid_sources[0x57]	291088	1			T5	6		T7	4		T11	109
valid_sources[0x58]	277718	1			T5	7		T6	1		T7	3
valid_sources[0x59]	284074	1			T5	13		T7	1		T11	82
valid_sources[0x5a]	306839	1			T3	8		T5	6		T7	2
valid_sources[0x5b]	271774	1			T5	3		T6	3		T11	96
valid_sources[0x5c]	321094	1			T5	5		T12	35		T22	4
valid_sources[0x5d]	256393	1			T5	6		T7	10		T11	13
valid_sources[0x5e]	281563	1			T5	14		T7	4		T11	13
valid_sources[0x5f]	257410	1			T4	223		T5	6		T6	2
valid_sources[0x60]	290623	1			T2	1		T5	11		T6	2
valid_sources[0x61]	281607	1			T5	8		T6	1		T7	2
valid_sources[0x62]	265768	1			T2	1		T5	12		T6	3
valid_sources[0x63]	266607	1			T2	1		T5	12		T7	1
valid_sources[0x64]	309478	1			T5	14		T6	2		T7	2
valid_sources[0x65]	313909	1			T5	9		T6	2		T7	1
valid_sources[0x66]	274882	1			T2	3		T5	7		T7	9
valid_sources[0x67]	266099	1			T5	5		T7	6		T11	16
valid_sources[0x68]	343301	1			T2	4		T5	17		T6	1
valid_sources[0x69]	258696	1			T5	10		T7	6		T11	25
valid_sources[0x6a]	307622	1			T5	14		T6	2		T7	1
valid_sources[0x6b]	282393	1			T5	9		T7	2		T11	14
valid_sources[0x6c]	255775	1			T1	98		T5	14		T7	1
valid_sources[0x6d]	343811	1			T2	1		T5	10		T6	2
valid_sources[0x6e]	302781	1			T5	5		T7	1		T11	18
valid_sources[0x6f]	273520	1			T2	1		T5	10		T6	1
valid_sources[0x70]	321240	1			T5	12		T7	3		T11	14
valid_sources[0x71]	302309	1			T5	7		T6	1		T7	7
valid_sources[0x72]	317829	1			T5	13		T11	25		T12	53
valid_sources[0x73]	275114	1			T5	12		T7	3		T12	41
valid_sources[0x74]	284363	1			T2	2		T5	6		T7	3
valid_sources[0x75]	274665	1			T2	2		T5	6		T6	1
valid_sources[0x76]	330268	1			T5	9		T6	2		T7	4
valid_sources[0x77]	262740	1			T5	5		T7	2		T11	13
valid_sources[0x78]	309585	1			T5	8		T6	4		T7	3
valid_sources[0x79]	316102	1			T5	10		T6	1		T7	1
valid_sources[0x7a]	514201	1			T5	9		T7	5		T11	136
valid_sources[0x7b]	256382	1			T2	5		T5	9		T6	1
valid_sources[0x7c]	315165	1			T5	7		T6	2		T7	7
valid_sources[0x7d]	279076	1			T5	9		T6	2		T7	1
valid_sources[0x7e]	291471	1			T3	9		T5	5		T7	7
valid_sources[0x7f]	288936	1			T5	9		T7	1		T12	15
valid_sources[0x80]	294781	1			T5	10		T6	1		T7	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

13291226

1

T1

7

T2

26

T3

4

values[0x0]

all_enables

biggest_size

416698

1

T1

5

T2

8

T3

9

values[0x1]

all_enables

biggest_size

368337

1

T1

4

T2

5

T3

1