Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/uart-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	1001956	0	0
ctrl_rd_A	2147483647	23298	0	0
intr_enable_rd_A	2147483647	21032	0	0
ovrd_rd_A	2147483647	21252	0	0
timeout_ctrl_rd_A	2147483647	22353	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1001956	0	0
T12	201423	9933	0	0
T13	980604	0	0	0
T22	47332	0	0	0
T25	132169	0	0	0
T28	0	3168	0	0
T29	983787	0	0	0
T30	0	8437	0	0
T31	5048	0	0	0
T33	1011	0	0	0
T36	0	5012	0	0
T37	0	5600	0	0
T38	0	13747	0	0
T39	0	3534	0	0
T40	0	7481	0	0
T41	0	19939	0	0
T42	0	12183	0	0
T43	309473	0	0	0
T44	5864	0	0	0
T45	36088	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	23298	0	0
T21	172108	0	0	0
T37	260583	584	0	0
T39	0	483	0	0
T42	0	425	0	0
T52	94550	0	0	0
T88	0	179	0	0
T89	0	1088	0	0
T90	0	436	0	0
T91	0	909	0	0
T92	0	832	0	0
T93	0	272	0	0
T94	0	259	0	0
T95	22241	0	0	0
T96	23991	0	0	0
T97	154351	0	0	0
T98	132828	0	0	0
T99	386596	0	0	0
T100	1106	0	0	0
T101	281876	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21032	0	0
T21	172108	0	0	0
T37	260583	597	0	0
T39	0	389	0	0
T42	0	309	0	0
T52	94550	0	0	0
T88	0	186	0	0
T89	0	778	0	0
T90	0	255	0	0
T91	0	838	0	0
T92	0	673	0	0
T93	0	259	0	0
T94	0	237	0	0
T95	22241	0	0	0
T96	23991	0	0	0
T97	154351	0	0	0
T98	132828	0	0	0
T99	386596	0	0	0
T100	1106	0	0	0
T101	281876	0	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21252	0	0
T21	172108	0	0	0
T37	260583	643	0	0
T39	0	470	0	0
T42	0	433	0	0
T52	94550	0	0	0
T88	0	231	0	0
T89	0	895	0	0
T90	0	264	0	0
T91	0	831	0	0
T92	0	675	0	0
T93	0	334	0	0
T94	0	265	0	0
T95	22241	0	0	0
T96	23991	0	0	0
T97	154351	0	0	0
T98	132828	0	0	0
T99	386596	0	0	0
T100	1106	0	0	0
T101	281876	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22353	0	0
T21	172108	0	0	0
T37	260583	761	0	0
T39	0	421	0	0
T42	0	383	0	0
T52	94550	0	0	0
T88	0	182	0	0
T89	0	867	0	0
T90	0	362	0	0
T91	0	963	0	0
T92	0	770	0	0
T93	0	276	0	0
T94	0	190	0	0
T95	22241	0	0	0
T96	23991	0	0	0
T97	154351	0	0	0
T98	132828	0	0	0
T99	386596	0	0	0
T100	1106	0	0	0
T101	281876	0	0	0