Line Coverage for Module :
uart_tx
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 29 | 29 | 100.00 |
| CONT_ASSIGN | 32 | 1 | 1 | 100.00 |
| ALWAYS | 35 | 6 | 6 | 100.00 |
| ALWAYS | 46 | 7 | 7 | 100.00 |
| ALWAYS | 58 | 14 | 14 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
31
32 1/1 assign tx = tx_q;
Tests: T1 T2 T3
33
34 always_ff @(posedge clk_i or negedge rst_ni) begin
35 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
36 1/1 baud_div_q <= 4'h0;
Tests: T1 T2 T3
37 1/1 tick_baud_q <= 1'b0;
Tests: T1 T2 T3
38 1/1 end else if (tick_baud_x16) begin
Tests: T1 T2 T3
39 1/1 {tick_baud_q, baud_div_q} <= {1'b0,baud_div_q} + 5'h1;
Tests: T1 T4 T5
40 end else begin
41 1/1 tick_baud_q <= 1'b0;
Tests: T1 T2 T3
42 end
43 end
44
45 always_ff @(posedge clk_i or negedge rst_ni) begin
46 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
47 1/1 bit_cnt_q <= 4'h0;
Tests: T1 T2 T3
48 1/1 sreg_q <= 11'h7ff;
Tests: T1 T2 T3
49 1/1 tx_q <= 1'b1;
Tests: T1 T2 T3
50 end else begin
51 1/1 bit_cnt_q <= bit_cnt_d;
Tests: T1 T2 T3
52 1/1 sreg_q <= sreg_d;
Tests: T1 T2 T3
53 1/1 tx_q <= tx_d;
Tests: T1 T2 T3
54 end
55 end
56
57 always_comb begin
58 1/1 if (!tx_enable) begin
Tests: T1 T2 T3
59 1/1 bit_cnt_d = 4'h0;
Tests: T1 T2 T3
60 1/1 sreg_d = 11'h7ff;
Tests: T1 T2 T3
61 1/1 tx_d = 1'b1;
Tests: T1 T2 T3
62 end else begin
63 1/1 bit_cnt_d = bit_cnt_q;
Tests: T1 T4 T5
64 1/1 sreg_d = sreg_q;
Tests: T1 T4 T5
65 1/1 tx_d = tx_q;
Tests: T1 T4 T5
66 1/1 if (wr) begin
Tests: T1 T4 T5
67 1/1 sreg_d = {1'b1, (parity_enable ? wr_parity : 1'b1), wr_data, 1'b0};
Tests: T1 T4 T5
68 1/1 bit_cnt_d = (parity_enable ? 4'd11 : 4'd10);
Tests: T1 T4 T5
69 1/1 end else if (tick_baud_q && (bit_cnt_q != 4'h0)) begin
Tests: T1 T4 T5
70 1/1 sreg_d = {1'b1, sreg_q[10:1]};
Tests: T1 T4 T5
71 1/1 tx_d = sreg_q[0];
Tests: T1 T4 T5
72 1/1 bit_cnt_d = bit_cnt_q - 4'h1;
Tests: T1 T4 T5
73 end
MISSING_ELSE
74 end
75 end
76
77 1/1 assign idle = (tx_enable) ? (bit_cnt_q == 4'h0) : 1'b1;
Tests: T1 T2 T3
Cond Coverage for Module :
uart_tx
| Total | Covered | Percent |
|---|
| Conditions | 13 | 13 | 100.00 |
| Logical | 13 | 13 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 67
SUB-EXPRESSION (parity_enable ? wr_parity : 1'b1)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T1,T4,T5 |
LINE 68
EXPRESSION (parity_enable ? 4'd11 : 4'd10)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T1,T4,T5 |
LINE 69
EXPRESSION (tick_baud_q && (bit_cnt_q != 4'b0))
-----1----- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 69
SUB-EXPRESSION (bit_cnt_q != 4'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T1,T4,T5 |
LINE 77
EXPRESSION (tx_enable ? (bit_cnt_q == 4'b0) : 1'b1)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T4,T5 |
LINE 77
SUB-EXPRESSION (bit_cnt_q == 4'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T1,T4,T5 |
Branch Coverage for Module :
uart_tx
| Line No. | Total | Covered | Percent |
| Branches |
|
12 |
12 |
100.00 |
| TERNARY |
77 |
2 |
2 |
100.00 |
| IF |
35 |
3 |
3 |
100.00 |
| IF |
46 |
2 |
2 |
100.00 |
| IF |
58 |
5 |
5 |
100.00 |
77 assign idle = (tx_enable) ? (bit_cnt_q == 4'h0) : 1'b1;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
35 if (!rst_ni) begin
-1-
36 baud_div_q <= 4'h0;
==>
37 tick_baud_q <= 1'b0;
38 end else if (tick_baud_x16) begin
-2-
39 {tick_baud_q, baud_div_q} <= {1'b0,baud_div_q} + 5'h1;
==>
40 end else begin
41 tick_baud_q <= 1'b0;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T4,T5 |
| 0 |
0 |
Covered |
T1,T2,T3 |
46 if (!rst_ni) begin
-1-
47 bit_cnt_q <= 4'h0;
==>
48 sreg_q <= 11'h7ff;
49 tx_q <= 1'b1;
50 end else begin
51 bit_cnt_q <= bit_cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
58 if (!tx_enable) begin
-1-
59 bit_cnt_d = 4'h0;
==>
60 sreg_d = 11'h7ff;
61 tx_d = 1'b1;
62 end else begin
63 bit_cnt_d = bit_cnt_q;
64 sreg_d = sreg_q;
65 tx_d = tx_q;
66 if (wr) begin
-2-
67 sreg_d = {1'b1, (parity_enable ? wr_parity : 1'b1), wr_data, 1'b0};
68 bit_cnt_d = (parity_enable ? 4'd11 : 4'd10);
-3-
==>
==>
69 end else if (tick_baud_q && (bit_cnt_q != 4'h0)) begin
-4-
70 sreg_d = {1'b1, sreg_q[10:1]};
==>
71 tx_d = sreg_q[0];
72 bit_cnt_d = bit_cnt_q - 4'h1;
73 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
1 |
- |
Covered |
T1,T4,T5 |
| 0 |
1 |
0 |
- |
Covered |
T1,T4,T5 |
| 0 |
0 |
- |
1 |
Covered |
T1,T4,T5 |
| 0 |
0 |
- |
0 |
Covered |
T1,T4,T5 |
