Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	57699593	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

11916670

1

T1

9

T2

24

T3

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	68426039	1			T1	32		T2	902		T3	5346
values[0x0]	577372	1			T1	5		T2	30		T3	8
values[0x1]	612852	1			T1	8		T2	26		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39718368	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

29897895

1

T1

20

T2

317

T3

2714

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	254489	1			T3	23		T8	9		T16	8
valid_sources[0x01]	235235	1			T2	13		T3	14		T7	20
valid_sources[0x02]	235346	1			T3	10		T7	1		T8	5
valid_sources[0x03]	285930	1			T3	27		T8	12		T16	7
valid_sources[0x04]	264058	1			T2	11		T3	17		T7	7
valid_sources[0x05]	265768	1			T3	25		T8	6		T16	4
valid_sources[0x06]	285523	1			T3	18		T8	5		T16	3
valid_sources[0x07]	251009	1			T2	6		T3	22		T7	5
valid_sources[0x08]	270171	1			T2	2		T3	26		T8	8
valid_sources[0x09]	241038	1			T3	19		T8	10		T16	5
valid_sources[0x0a]	255386	1			T1	45		T2	9		T3	24
valid_sources[0x0b]	273358	1			T3	20		T8	4		T16	6
valid_sources[0x0c]	289553	1			T3	16		T7	5		T8	6
valid_sources[0x0d]	281423	1			T3	21		T7	1		T8	11
valid_sources[0x0e]	240549	1			T3	23		T7	12		T8	13
valid_sources[0x0f]	272506	1			T2	17		T3	13		T7	4
valid_sources[0x10]	262696	1			T3	16		T8	6		T16	7
valid_sources[0x11]	257431	1			T3	18		T7	2		T8	4
valid_sources[0x12]	262945	1			T2	8		T3	24		T7	11
valid_sources[0x13]	241744	1			T3	20		T7	13		T8	12
valid_sources[0x14]	270221	1			T3	23		T7	3		T8	5
valid_sources[0x15]	319536	1			T2	11		T3	29		T7	2
valid_sources[0x16]	239046	1			T2	2		T3	17		T8	7
valid_sources[0x17]	236426	1			T3	20		T7	11		T8	3
valid_sources[0x18]	261033	1			T3	15		T7	6		T8	4
valid_sources[0x19]	254535	1			T3	16		T7	16		T8	13
valid_sources[0x1a]	242322	1			T3	15		T8	5		T12	13
valid_sources[0x1b]	248947	1			T2	1		T3	24		T7	10
valid_sources[0x1c]	284050	1			T3	25		T7	4		T8	4
valid_sources[0x1d]	246755	1			T2	16		T3	28		T7	9
valid_sources[0x1e]	272359	1			T2	2		T3	31		T8	8
valid_sources[0x1f]	244434	1			T2	13		T3	16		T7	13
valid_sources[0x20]	289142	1			T3	17		T7	1		T8	5
valid_sources[0x21]	249511	1			T3	12		T7	5		T8	7
valid_sources[0x22]	283853	1			T2	19		T3	19		T8	6
valid_sources[0x23]	246733	1			T3	24		T7	34		T8	7
valid_sources[0x24]	237805	1			T3	8		T7	20		T8	10
valid_sources[0x25]	247825	1			T2	12		T3	23		T7	17
valid_sources[0x26]	263435	1			T2	11		T3	19		T7	2
valid_sources[0x27]	243241	1			T2	1		T3	31		T7	1
valid_sources[0x28]	253397	1			T3	22		T7	8		T8	11
valid_sources[0x29]	272778	1			T2	19		T3	22		T7	19
valid_sources[0x2a]	242736	1			T3	19		T7	8		T8	5
valid_sources[0x2b]	258093	1			T2	33		T3	19		T7	11
valid_sources[0x2c]	258581	1			T3	20		T7	6		T8	7
valid_sources[0x2d]	270002	1			T2	11		T3	16		T7	6
valid_sources[0x2e]	256394	1			T2	23		T3	17		T7	12
valid_sources[0x2f]	249788	1			T3	22		T8	6		T16	8
valid_sources[0x30]	250786	1			T3	29		T7	13		T8	7
valid_sources[0x31]	256179	1			T2	10		T3	18		T7	2
valid_sources[0x32]	256729	1			T3	23		T7	29		T8	13
valid_sources[0x33]	356615	1			T3	24		T7	32		T8	3
valid_sources[0x34]	344470	1			T3	21		T7	4		T8	7
valid_sources[0x35]	282197	1			T2	10		T3	25		T7	9
valid_sources[0x36]	299635	1			T3	26		T8	11		T16	11
valid_sources[0x37]	237465	1			T3	18		T7	1		T8	7
valid_sources[0x38]	298581	1			T2	9		T3	21		T7	4
valid_sources[0x39]	253189	1			T3	20		T7	12		T8	9
valid_sources[0x3a]	251601	1			T3	13		T7	1		T8	7
valid_sources[0x3b]	268273	1			T3	17		T8	6		T16	2
valid_sources[0x3c]	456208	1			T2	2		T3	16		T7	25
valid_sources[0x3d]	270905	1			T3	27		T7	19		T8	9
valid_sources[0x3e]	304798	1			T3	10		T7	10		T8	11
valid_sources[0x3f]	229471	1			T3	15		T7	2		T8	8
valid_sources[0x40]	288313	1			T3	27		T7	3		T8	8
valid_sources[0x41]	271549	1			T3	18		T7	4		T8	9
valid_sources[0x42]	253933	1			T2	18		T3	21		T7	28
valid_sources[0x43]	242033	1			T3	25		T7	1		T8	9
valid_sources[0x44]	252246	1			T3	20		T7	28		T8	8
valid_sources[0x45]	279037	1			T2	7		T3	29		T5	223
valid_sources[0x46]	289114	1			T2	1		T3	26		T7	21
valid_sources[0x47]	252120	1			T2	7		T3	24		T8	4
valid_sources[0x48]	260839	1			T3	26		T7	7		T8	4
valid_sources[0x49]	304260	1			T2	7		T3	18		T7	7
valid_sources[0x4a]	264158	1			T2	12		T3	19		T8	5
valid_sources[0x4b]	259992	1			T2	18		T3	21		T7	16
valid_sources[0x4c]	270712	1			T3	18		T8	9		T16	1
valid_sources[0x4d]	281903	1			T2	15		T3	20		T7	1
valid_sources[0x4e]	259638	1			T2	3		T3	26		T7	1
valid_sources[0x4f]	332144	1			T3	18		T8	7		T16	9
valid_sources[0x50]	257859	1			T3	18		T7	5		T8	6
valid_sources[0x51]	251489	1			T3	22		T7	5		T8	13
valid_sources[0x52]	262202	1			T2	13		T3	19		T7	26
valid_sources[0x53]	261360	1			T2	5		T3	18		T7	1
valid_sources[0x54]	277630	1			T3	19		T7	8		T8	7
valid_sources[0x55]	270684	1			T3	28		T7	6		T8	8
valid_sources[0x56]	253401	1			T3	20		T4	1		T7	6
valid_sources[0x57]	241625	1			T3	24		T7	2		T8	12
valid_sources[0x58]	338574	1			T2	4		T3	14		T7	6
valid_sources[0x59]	254505	1			T3	11		T7	7		T8	7
valid_sources[0x5a]	253780	1			T3	25		T7	10		T8	9
valid_sources[0x5b]	284312	1			T2	2		T3	22		T7	5
valid_sources[0x5c]	263670	1			T3	24		T7	1		T8	11
valid_sources[0x5d]	295491	1			T3	14		T8	11		T16	4
valid_sources[0x5e]	325281	1			T3	28		T7	20		T8	8
valid_sources[0x5f]	312857	1			T3	21		T7	20		T8	6
valid_sources[0x60]	242060	1			T3	18		T7	5		T8	8
valid_sources[0x61]	250653	1			T2	21		T3	18		T7	12
valid_sources[0x62]	327277	1			T3	26		T7	4		T8	9
valid_sources[0x63]	282480	1			T3	25		T7	12		T8	8
valid_sources[0x64]	290132	1			T3	21		T8	9		T16	5
valid_sources[0x65]	265777	1			T3	16		T7	17		T8	5
valid_sources[0x66]	290993	1			T3	21		T7	2		T8	8
valid_sources[0x67]	243331	1			T2	7		T3	17		T7	29
valid_sources[0x68]	300472	1			T3	16		T7	12		T8	9
valid_sources[0x69]	435759	1			T3	16		T7	2		T8	8
valid_sources[0x6a]	247348	1			T3	18		T8	5		T16	2
valid_sources[0x6b]	264403	1			T3	20		T7	8		T8	3
valid_sources[0x6c]	265428	1			T2	1		T3	25		T7	8
valid_sources[0x6d]	417188	1			T2	6		T3	23		T8	3
valid_sources[0x6e]	312515	1			T3	23		T7	8		T8	5
valid_sources[0x6f]	330277	1			T3	21		T7	17		T8	8
valid_sources[0x70]	251649	1			T2	7		T3	16		T7	4
valid_sources[0x71]	256410	1			T2	3		T3	29		T7	16
valid_sources[0x72]	519233	1			T2	5		T3	20		T7	3
valid_sources[0x73]	253103	1			T3	26		T7	10		T8	8
valid_sources[0x74]	266213	1			T2	4		T3	17		T7	14
valid_sources[0x75]	256844	1			T2	27		T3	14		T8	10
valid_sources[0x76]	269250	1			T3	11		T8	13		T9	1
valid_sources[0x77]	309988	1			T2	8		T3	25		T8	10
valid_sources[0x78]	260678	1			T2	3		T3	19		T7	7
valid_sources[0x79]	246798	1			T3	27		T8	14		T16	7
valid_sources[0x7a]	241010	1			T3	31		T7	1		T8	7
valid_sources[0x7b]	243281	1			T2	16		T3	26		T7	3
valid_sources[0x7c]	242772	1			T2	5		T3	23		T7	4
valid_sources[0x7d]	268934	1			T3	30		T7	8		T8	13
valid_sources[0x7e]	260097	1			T2	1		T3	15		T7	3
valid_sources[0x7f]	254384	1			T3	22		T7	5		T8	8
valid_sources[0x80]	253790	1			T3	24		T7	16		T8	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

11152912

1

T1

5

T2

5

T4

1

values[0x0]

all_enables

biggest_size

405857

1

T1

1

T2

11

T3

3

values[0x1]

all_enables

biggest_size

357901

1

T1

3

T2

8

T3

9