Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/uart-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	968220	0	0
ctrl_rd_A	2147483647	18458	0	0
intr_enable_rd_A	2147483647	17351	0	0
ovrd_rd_A	2147483647	17330	0	0
timeout_ctrl_rd_A	2147483647	17753	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	968220	0	0
T19	173658	3035	0	0
T20	0	22646	0	0
T23	346560	0	0	0
T26	429275	0	0	0
T27	0	11392	0	0
T30	0	14166	0	0
T31	0	2712	0	0
T32	0	12799	0	0
T33	0	5601	0	0
T34	0	1158	0	0
T35	0	9072	0	0
T36	0	6792	0	0
T37	791461	0	0	0
T38	4694	0	0	0
T39	623558	0	0	0
T40	304512	0	0	0
T41	67379	0	0	0
T42	137011	0	0	0
T43	361125	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	18458	0	0
T19	173658	387	0	0
T23	346560	0	0	0
T26	429275	0	0	0
T31	0	379	0	0
T32	0	636	0	0
T34	0	152	0	0
T35	0	973	0	0
T37	791461	0	0	0
T38	4694	0	0	0
T39	623558	0	0	0
T40	304512	0	0	0
T41	67379	0	0	0
T42	137011	0	0	0
T43	361125	0	0	0
T78	0	724	0	0
T79	0	552	0	0
T80	0	449	0	0
T81	0	1139	0	0
T82	0	1313	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	17351	0	0
T19	173658	431	0	0
T23	346560	0	0	0
T26	429275	0	0	0
T31	0	226	0	0
T32	0	555	0	0
T34	0	147	0	0
T35	0	908	0	0
T37	791461	0	0	0
T38	4694	0	0	0
T39	623558	0	0	0
T40	304512	0	0	0
T41	67379	0	0	0
T42	137011	0	0	0
T43	361125	0	0	0
T78	0	790	0	0
T79	0	392	0	0
T80	0	528	0	0
T81	0	1264	0	0
T82	0	1038	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	17330	0	0
T19	173658	516	0	0
T23	346560	0	0	0
T26	429275	0	0	0
T31	0	298	0	0
T32	0	620	0	0
T34	0	110	0	0
T35	0	953	0	0
T37	791461	0	0	0
T38	4694	0	0	0
T39	623558	0	0	0
T40	304512	0	0	0
T41	67379	0	0	0
T42	137011	0	0	0
T43	361125	0	0	0
T78	0	718	0	0
T79	0	445	0	0
T80	0	454	0	0
T81	0	1404	0	0
T82	0	1150	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	17753	0	0
T19	173658	444	0	0
T23	346560	0	0	0
T26	429275	0	0	0
T31	0	299	0	0
T32	0	627	0	0
T34	0	153	0	0
T35	0	1022	0	0
T37	791461	0	0	0
T38	4694	0	0	0
T39	623558	0	0	0
T40	304512	0	0	0
T41	67379	0	0	0
T42	137011	0	0	0
T43	361125	0	0	0
T78	0	773	0	0
T79	0	464	0	0
T80	0	510	0	0
T81	0	1476	0	0
T82	0	1356	0	0