Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	89781	1			T1	2		T2	1		T3	2
all_values[1]	89781	1			T1	2		T2	1		T3	2
all_values[2]	89781	1			T1	2		T2	1		T3	2
all_values[3]	89781	1			T1	2		T2	1		T3	2
all_values[4]	89781	1			T1	2		T2	1		T3	2
all_values[5]	89781	1			T1	2		T2	1		T3	2
all_values[6]	89781	1			T1	2		T2	1		T3	2
all_values[7]	89781	1			T1	2		T2	1		T3	2
all_values[8]	89781	1			T1	2		T2	1		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

402114

1

T1

18

T2

6

T3

18

auto[1]

405915

1

T2

3

T7

4

T8

41

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

732604

1

T1

13

T2

7

T3

13

auto[1]

75425

1

T1

5

T2

2

T3

5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	27112	1			T11	20		T12	3		T21	1
all_values[0]	auto[0]	auto[1]	17167	1			T1	2		T3	2		T4	2
all_values[0]	auto[1]	auto[0]	26251	1			T45	2		T28	16		T21	3
all_values[0]	auto[1]	auto[1]	19251	1			T2	1		T8	7		T15	1
all_values[1]	auto[0]	auto[0]	44189	1			T1	2		T3	2		T4	2
all_values[1]	auto[0]	auto[1]	1638	1			T21	17		T17	3		T46	2
all_values[1]	auto[1]	auto[0]	42418	1			T2	1		T11	10		T12	3
all_values[1]	auto[1]	auto[1]	1536	1			T28	8		T13	1		T22	18
all_values[2]	auto[0]	auto[0]	39472	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	2452	1			T1	1		T3	1		T4	1
all_values[2]	auto[1]	auto[0]	45841	1			T7	1		T10	1		T11	6
all_values[2]	auto[1]	auto[1]	2016	1			T11	4		T12	2		T28	1
all_values[3]	auto[0]	auto[0]	43442	1			T1	2		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	237	1			T20	1		T17	1		T18	1
all_values[3]	auto[1]	auto[0]	45871	1			T7	1		T10	1		T15	1
all_values[3]	auto[1]	auto[1]	231	1			T20	2		T19	2		T46	1
all_values[4]	auto[0]	auto[0]	44082	1			T1	2		T2	1		T3	2
all_values[4]	auto[0]	auto[1]	422	1			T20	3		T22	11		T24	4
all_values[4]	auto[1]	auto[0]	44973	1			T8	9		T10	1		T15	1
all_values[4]	auto[1]	auto[1]	304	1			T21	4		T24	1		T76	1
all_values[5]	auto[0]	auto[0]	39898	1			T1	2		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	168	1			T20	4		T38	5		T73	3
all_values[5]	auto[1]	auto[0]	49575	1			T7	1		T8	7		T10	1
all_values[5]	auto[1]	auto[1]	140	1			T38	3		T73	1		T109	1
all_values[6]	auto[0]	auto[0]	45477	1			T1	2		T3	2		T4	2
all_values[6]	auto[0]	auto[1]	118	1			T20	2		T38	3		T73	1
all_values[6]	auto[1]	auto[0]	44023	1			T2	1		T7	1		T8	9
all_values[6]	auto[1]	auto[1]	163	1			T20	1		T38	5		T109	1
all_values[7]	auto[0]	auto[0]	47227	1			T1	2		T2	1		T3	2
all_values[7]	auto[0]	auto[1]	296	1			T20	2		T26	1		T17	1
all_values[7]	auto[1]	auto[0]	41991	1			T8	7		T10	1		T15	1
all_values[7]	auto[1]	auto[1]	267	1			T21	4		T20	5		T102	1
all_values[8]	auto[0]	auto[0]	34314	1			T11	7		T12	3		T28	16
all_values[8]	auto[0]	auto[1]	14403	1			T1	2		T2	1		T3	2
all_values[8]	auto[1]	auto[0]	26448	1			T11	13		T12	1		T45	4
all_values[8]	auto[1]	auto[1]	14616	1			T8	2		T11	10		T12	2