Total Groups Coverage Summary 

COVERED	EXPECTED	SCORE	COVERED	EXPECTED	INST SCORE	WEIGHT
4405	4429	99.46	4405	4429	99.46	1

Total groups in report: 22

---

NAME	COVERED	EXPECTED	SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING	COMMENT
tl_agent_pkg::pending_req_on_rst_cg	1	2	50.00	50.00	1	100	1	1	64	64
uart_env_pkg::uart_env_cov::tx_watermark_cg	5	7	71.43		1	100	1	0	64	64
cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg	12	15	80.00	100.00	1	100	1	1	64	64
uart_env_pkg::uart_env_cov::rx_watermark_cg	7	8	87.50		1	100	1	0	64	64
cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}	63	69	91.30		1	100	1	0	64	64
cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg	13	14	92.86	100.00	1	100	1	1	64	64
uart_env_pkg::uart_env_cov::rx_fifo_level_cg	183	197	92.89		1	100	1	0	64	64
alert_esc_agent_pkg::alert_handshake_complete_cg	3	3	100.00	100.00	1	100	1	1	64	64
cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}	49	49	100.00		1	100	1	0	64	64
cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}	49	49	100.00		1	100	1	0	64	64
dv_lib_pkg::bit_toggle_cg_wrap::bit_toggle_cg	4	4	100.00	100.00	1	100	1	1	64	64
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check.u_prim_onehot_check_if::prim_onehot_check_without_addr_fault_if_proxy::onehot_without_addr_fault_cg	2	2	100.00	100.00	1	100	1	1	64	64
tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=1}	1	1	100.00	100.00	1	100	1	1	64	64
tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}	137	137	100.00	100.00	1	100	1	1	64	64
uart_agent_pkg::uart_agent_cov::uart_cg	3661	3661	100.00		1	100	1	0	64	64
uart_agent_pkg::uart_agent_cov::uart_reset_cg	35	35	100.00		1	100	1	0	64	64
uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg	46	46	100.00		1	100	1	0	64	64
uart_env_pkg::uart_env_cov::noise_filter_cg	8	8	100.00		1	100	1	0	64	64
uart_env_pkg::uart_env_cov::rx_break_err_cg	4	4	100.00		1	100	1	0	64	64
uart_env_pkg::uart_env_cov::rx_parity_err_cg	2	2	100.00		1	100	1	0	64	64
uart_env_pkg::uart_env_cov::rx_timeout_cg	3	3	100.00		1	100	1	0	64	64
uart_env_pkg::uart_env_cov::tx_fifo_level_cg	101	101	100.00		1	100	1	0	64	64