Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1850	1			T2	3		T7	3		T8	1
auto[BaudRate115200]	1567	1			T7	3		T8	1		T14	1
auto[BaudRate230400]	1619	1			T1	1		T7	6		T8	3
auto[BaudRate128Kbps]	1552	1			T3	2		T4	1		T8	1
auto[BaudRate256Kbps]	1753	1			T7	15		T8	2		T9	1
auto[BaudRate1Mbps]	1451	1			T1	1		T7	12		T8	3
auto[BaudRate1p5Mbps]	1133	1			T4	1		T7	3		T12	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	915	1			T12	7		T17	6		T75	13
freqs[25]	895	1			T8	11		T352	2		T33	9
freqs[48]	403	1			T9	2		T36	18		T399	12
freqs[50]	589	1			T1	2		T400	1		T27	7
freqs[100]	992	1			T3	2		T16	2		T44	2

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	188	1			T75	13		T125	1		T73	1
auto[BaudRate9600]	freqs[25]	158	1			T8	1		T33	2		T401	9
auto[BaudRate9600]	freqs[48]	85	1			T9	1		T399	12		T402	3
auto[BaudRate9600]	freqs[50]	102	1			T400	1		T403	18		T277	1
auto[BaudRate9600]	freqs[100]	171	1			T40	4		T101	1		T280	1
auto[BaudRate115200]	freqs[24]	139	1			T12	3		T97	1		T73	4
auto[BaudRate115200]	freqs[25]	114	1			T8	1		T33	2		T401	6
auto[BaudRate115200]	freqs[48]	58	1			T36	1		T402	6		T134	2
auto[BaudRate115200]	freqs[50]	88	1			T403	3		T135	2		T158	1
auto[BaudRate115200]	freqs[100]	136	1			T44	1		T28	1		T13	2
auto[BaudRate230400]	freqs[24]	142	1			T12	2		T17	2		T97	1
auto[BaudRate230400]	freqs[25]	112	1			T8	3		T33	1		T401	3
auto[BaudRate230400]	freqs[48]	50	1			T36	2		T402	3		T372	1
auto[BaudRate230400]	freqs[50]	76	1			T1	1		T27	1		T403	6
auto[BaudRate230400]	freqs[100]	125	1			T28	2		T13	1		T43	2
auto[BaudRate128Kbps]	freqs[24]	111	1			T17	1		T125	2		T73	6
auto[BaudRate128Kbps]	freqs[25]	144	1			T8	1		T401	9		T104	2
auto[BaudRate128Kbps]	freqs[48]	48	1			T36	4		T297	1		T370	1
auto[BaudRate128Kbps]	freqs[50]	56	1			T403	6		T277	1		T290	1
auto[BaudRate128Kbps]	freqs[100]	124	1			T3	2		T16	1		T13	1
auto[BaudRate256Kbps]	freqs[24]	125	1			T320	1		T271	2		T125	1
auto[BaudRate256Kbps]	freqs[25]	155	1			T8	2		T352	1		T33	1
auto[BaudRate256Kbps]	freqs[48]	52	1			T9	1		T36	6		T297	3
auto[BaudRate256Kbps]	freqs[50]	93	1			T27	5		T403	3		T264	1
auto[BaudRate256Kbps]	freqs[100]	155	1			T16	1		T43	4		T298	1
auto[BaudRate1Mbps]	freqs[24]	125	1			T17	2		T271	1		T73	2
auto[BaudRate1Mbps]	freqs[25]	135	1			T8	3		T33	2		T401	6
auto[BaudRate1Mbps]	freqs[48]	59	1			T36	4		T297	1		T402	3
auto[BaudRate1Mbps]	freqs[50]	88	1			T1	1		T27	1		T403	6
auto[BaudRate1Mbps]	freqs[100]	160	1			T28	1		T43	4		T102	3
auto[BaudRate1p5Mbps]	freqs[25]	77	1			T352	1		T33	1		T104	1
auto[BaudRate1p5Mbps]	freqs[48]	51	1			T36	1		T402	6		T134	2
auto[BaudRate1p5Mbps]	freqs[50]	86	1			T403	12		T277	1		T272	2
auto[BaudRate1p5Mbps]	freqs[100]	121	1			T44	1		T28	1		T13	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded