Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.89	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	14	116	89.23

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	14	116	89.23	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	26816538	1			T2	1		T7	6		T8	97
all_levels[1]	174185	1			T8	10		T11	3		T28	2
all_levels[2]	2173	1			T8	4		T28	1		T13	2
all_levels[3]	860	1			T8	2		T11	4		T28	1
all_levels[4]	563	1			T8	2		T11	2		T12	1
all_levels[5]	407	1			T8	2		T11	1		T28	1
all_levels[6]	310	1			T11	2		T28	2		T43	1
all_levels[7]	239	1			T11	1		T28	2		T43	1
all_levels[8]	231	1			T8	2		T12	1		T28	1
all_levels[9]	169	1			T28	1		T13	1		T43	1
all_levels[10]	175	1			T8	1		T13	1		T43	1
all_levels[11]	161	1			T13	3		T18	1		T46	1
all_levels[12]	137	1			T43	1		T17	1		T102	1
all_levels[13]	128	1			T26	1		T49	2		T118	1
all_levels[14]	126	1			T12	1		T28	1		T13	1
all_levels[15]	91	1			T28	1		T46	1		T119	1
all_levels[16]	72	1			T28	1		T46	1		T120	1
all_levels[17]	108	1			T102	1		T103	1		T120	1
all_levels[18]	72	1			T49	1		T121	1		T122	1
all_levels[19]	75	1			T17	1		T103	1		T123	1
all_levels[20]	70	1			T28	1		T13	1		T118	1
all_levels[21]	41	1			T118	1		T124	1		T121	1
all_levels[22]	51	1			T102	1		T103	1		T121	1
all_levels[23]	57	1			T102	1		T49	1		T94	1
all_levels[24]	42	1			T13	2		T125	1		T119	1
all_levels[25]	54	1			T118	1		T95	1		T125	1
all_levels[26]	27	1			T13	1		T49	1		T126	1
all_levels[27]	48	1			T19	1		T103	1		T120	1
all_levels[28]	39	1			T28	1		T26	1		T46	1
all_levels[29]	33	1			T46	1		T120	1		T121	1
all_levels[30]	34	1			T127	1		T105	1		T128	1
all_levels[31]	40	1			T19	1		T118	1		T99	1
all_levels[32]	22	1			T122	1		T129	1		T130	1
all_levels[33]	23	1			T13	1		T120	1		T124	1
all_levels[34]	23	1			T126	1		T131	1		T132	1
all_levels[35]	30	1			T26	1		T49	2		T95	1
all_levels[36]	18	1			T12	1		T49	1		T133	1
all_levels[37]	16	1			T49	1		T118	1		T99	1
all_levels[38]	22	1			T26	1		T134	1		T131	1
all_levels[39]	18	1			T118	1		T121	3		T135	1
all_levels[40]	12	1			T18	2		T136	1		T132	1
all_levels[41]	9	1			T131	1		T137	1		T138	1
all_levels[42]	19	1			T121	1		T105	1		T139	1
all_levels[43]	12	1			T103	1		T140	1		T127	1
all_levels[44]	20	1			T127	1		T141	1		T142	1
all_levels[45]	7	1			T136	1		T143	1		T144	1
all_levels[46]	10	1			T104	1		T131	1		T145	1
all_levels[47]	13	1			T142	1		T146	1		T147	1
all_levels[48]	14	1			T120	1		T134	1		T148	1
all_levels[49]	8	1			T149	1		T150	1		T151	1
all_levels[50]	14	1			T152	1		T153	1		T145	1
all_levels[51]	12	1			T19	1		T99	1		T127	1
all_levels[52]	7	1			T127	1		T154	1		T155	1
all_levels[53]	9	1			T127	1		T133	1		T148	1
all_levels[54]	2	1			T102	1		T156	1		-	-
all_levels[55]	12	1			T157	1		T158	1		T131	1
all_levels[56]	9	1			T159	1		T160	1		T161	2
all_levels[57]	2	1			T162	1		T163	1		-	-
all_levels[58]	8	1			T17	1		T103	1		T134	1
all_levels[59]	6	1			T120	1		T34	1		T129	1
all_levels[60]	3	1			T164	1		T165	1		T166	1
all_levels[61]	4	1			T167	1		T168	1		T169	1
all_levels[62]	7	1			T170	1		T171	1		T172	2
all_levels[63]	10	1			T102	1		T136	3		T132	1
all_levels[64]	97	1			T17	2		T18	1		T19	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26993940

1

T8

120

T11

89

T12

27

auto[1]

3914

1

T2

1

T7

6

T10

1

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	14	116	89.23	14

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[21]]	[auto[1]]	0	1	1
[all_levels[35]]	[auto[1]]	0	1	1
[all_levels[41]]	[auto[1]]	0	1	1
[all_levels[43]]	[auto[1]]	0	1	1
[all_levels[49]]	[auto[1]]	0	1	1
[all_levels[52]]	[auto[1]]	0	1	1
[all_levels[54]]	[auto[1]]	0	1	1
[all_levels[56] , all_levels[57] , all_levels[58] , all_levels[59] , all_levels[60] , all_levels[61] , all_levels[62]]	[auto[1]]	--	--	7

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	26813019	1			T8	97		T11	76		T12	23
all_levels[0]	auto[1]	3519	1			T2	1		T7	6		T10	1
all_levels[1]	auto[0]	174108	1			T8	10		T11	3		T28	2
all_levels[1]	auto[1]	77	1			T103	1		T99	3		T142	1
all_levels[2]	auto[0]	2143	1			T8	4		T28	1		T13	2
all_levels[2]	auto[1]	30	1			T173	1		T174	1		T175	1
all_levels[3]	auto[0]	836	1			T8	2		T11	4		T28	1
all_levels[3]	auto[1]	24	1			T176	1		T177	1		T178	1
all_levels[4]	auto[0]	553	1			T8	2		T11	2		T12	1
all_levels[4]	auto[1]	10	1			T179	2		T180	3		T181	1
all_levels[5]	auto[0]	393	1			T8	2		T11	1		T28	1
all_levels[5]	auto[1]	14	1			T182	2		T183	1		T184	1
all_levels[6]	auto[0]	299	1			T11	2		T28	2		T43	1
all_levels[6]	auto[1]	11	1			T133	1		T185	3		T186	1
all_levels[7]	auto[0]	224	1			T11	1		T28	2		T43	1
all_levels[7]	auto[1]	15	1			T164	1		T187	1		T188	1
all_levels[8]	auto[0]	220	1			T8	2		T12	1		T28	1
all_levels[8]	auto[1]	11	1			T151	1		T189	2		T190	1
all_levels[9]	auto[0]	167	1			T28	1		T13	1		T43	1
all_levels[9]	auto[1]	2	1			T191	1		T192	1		-	-
all_levels[10]	auto[0]	166	1			T8	1		T13	1		T43	1
all_levels[10]	auto[1]	9	1			T193	1		T194	2		T195	1
all_levels[11]	auto[0]	150	1			T13	2		T18	1		T46	1
all_levels[11]	auto[1]	11	1			T13	1		T196	1		T178	1
all_levels[12]	auto[0]	131	1			T43	1		T17	1		T102	1
all_levels[12]	auto[1]	6	1			T99	1		T182	1		T197	1
all_levels[13]	auto[0]	122	1			T26	1		T49	2		T118	1
all_levels[13]	auto[1]	6	1			T198	1		T199	1		T200	1
all_levels[14]	auto[0]	115	1			T12	1		T28	1		T13	1
all_levels[14]	auto[1]	11	1			T201	1		T202	2		T203	2
all_levels[15]	auto[0]	83	1			T28	1		T46	1		T119	1
all_levels[15]	auto[1]	8	1			T204	1		T205	1		T147	1
all_levels[16]	auto[0]	70	1			T28	1		T46	1		T120	1
all_levels[16]	auto[1]	2	1			T175	1		T206	1		-	-
all_levels[17]	auto[0]	100	1			T102	1		T103	1		T120	1
all_levels[17]	auto[1]	8	1			T193	1		T207	1		T208	2
all_levels[18]	auto[0]	70	1			T49	1		T121	1		T122	1
all_levels[18]	auto[1]	2	1			T209	1		T192	1		-	-
all_levels[19]	auto[0]	65	1			T17	1		T103	1		T123	1
all_levels[19]	auto[1]	10	1			T128	2		T210	1		T144	1
all_levels[20]	auto[0]	60	1			T28	1		T13	1		T118	1
all_levels[20]	auto[1]	10	1			T127	2		T211	1		T212	3
all_levels[21]	auto[0]	41	1			T118	1		T124	1		T121	1
all_levels[22]	auto[0]	45	1			T102	1		T103	1		T121	1
all_levels[22]	auto[1]	6	1			T178	1		T213	3		T214	1
all_levels[23]	auto[0]	49	1			T102	1		T49	1		T94	1
all_levels[23]	auto[1]	8	1			T175	1		T190	2		T215	1
all_levels[24]	auto[0]	39	1			T13	2		T125	1		T119	1
all_levels[24]	auto[1]	3	1			T216	2		T217	1		-	-
all_levels[25]	auto[0]	48	1			T118	1		T95	1		T125	1
all_levels[25]	auto[1]	6	1			T218	1		T219	1		T220	1
all_levels[26]	auto[0]	26	1			T13	1		T49	1		T126	1
all_levels[26]	auto[1]	1	1			T221	1		-	-		-	-
all_levels[27]	auto[0]	45	1			T19	1		T103	1		T120	1
all_levels[27]	auto[1]	3	1			T222	3		-	-		-	-
all_levels[28]	auto[0]	35	1			T28	1		T26	1		T46	1
all_levels[28]	auto[1]	4	1			T142	1		T223	2		T224	1
all_levels[29]	auto[0]	30	1			T46	1		T120	1		T121	1
all_levels[29]	auto[1]	3	1			T225	1		T226	1		T227	1
all_levels[30]	auto[0]	31	1			T127	1		T105	1		T128	1
all_levels[30]	auto[1]	3	1			T228	1		T229	1		T230	1
all_levels[31]	auto[0]	34	1			T19	1		T118	1		T99	1
all_levels[31]	auto[1]	6	1			T211	1		T231	3		T232	1
all_levels[32]	auto[0]	20	1			T122	1		T129	1		T130	1
all_levels[32]	auto[1]	2	1			T233	2		-	-		-	-
all_levels[33]	auto[0]	18	1			T13	1		T120	1		T124	1
all_levels[33]	auto[1]	5	1			T234	4		T166	1		-	-
all_levels[34]	auto[0]	22	1			T126	1		T131	1		T132	1
all_levels[34]	auto[1]	1	1			T190	1		-	-		-	-
all_levels[35]	auto[0]	30	1			T26	1		T49	2		T95	1
all_levels[36]	auto[0]	16	1			T12	1		T49	1		T133	1
all_levels[36]	auto[1]	2	1			T235	1		T236	1		-	-
all_levels[37]	auto[0]	15	1			T49	1		T118	1		T99	1
all_levels[37]	auto[1]	1	1			T237	1		-	-		-	-
all_levels[38]	auto[0]	20	1			T26	1		T134	1		T131	1
all_levels[38]	auto[1]	2	1			T195	2		-	-		-	-
all_levels[39]	auto[0]	14	1			T118	1		T121	1		T135	1
all_levels[39]	auto[1]	4	1			T121	2		T238	2		-	-
all_levels[40]	auto[0]	9	1			T18	1		T136	1		T132	1
all_levels[40]	auto[1]	3	1			T18	1		T202	2		-	-
all_levels[41]	auto[0]	9	1			T131	1		T137	1		T138	1
all_levels[42]	auto[0]	16	1			T121	1		T105	1		T139	1
all_levels[42]	auto[1]	3	1			T239	1		T240	1		T224	1
all_levels[43]	auto[0]	12	1			T103	1		T140	1		T127	1
all_levels[44]	auto[0]	17	1			T127	1		T141	1		T142	1
all_levels[44]	auto[1]	3	1			T241	1		T242	1		T243	1
all_levels[45]	auto[0]	6	1			T136	1		T143	1		T144	1
all_levels[45]	auto[1]	1	1			T168	1		-	-		-	-
all_levels[46]	auto[0]	6	1			T104	1		T131	1		T145	1
all_levels[46]	auto[1]	4	1			T244	3		T203	1		-	-
all_levels[47]	auto[0]	10	1			T142	1		T146	1		T147	1
all_levels[47]	auto[1]	3	1			T245	1		T246	1		T168	1
all_levels[48]	auto[0]	11	1			T120	1		T134	1		T148	1
all_levels[48]	auto[1]	3	1			T247	2		T233	1		-	-
all_levels[49]	auto[0]	8	1			T149	1		T150	1		T151	1
all_levels[50]	auto[0]	10	1			T152	1		T153	1		T145	1
all_levels[50]	auto[1]	4	1			T248	3		T249	1		-	-
all_levels[51]	auto[0]	10	1			T19	1		T99	1		T127	1
all_levels[51]	auto[1]	2	1			T250	2		-	-		-	-
all_levels[52]	auto[0]	7	1			T127	1		T154	1		T155	1
all_levels[53]	auto[0]	8	1			T127	1		T133	1		T148	1
all_levels[53]	auto[1]	1	1			T251	1		-	-		-	-
all_levels[54]	auto[0]	2	1			T102	1		T156	1		-	-
all_levels[55]	auto[0]	8	1			T157	1		T158	1		T131	1
all_levels[55]	auto[1]	4	1			T252	2		T212	2		-	-
all_levels[56]	auto[0]	9	1			T159	1		T160	1		T161	2
all_levels[57]	auto[0]	2	1			T162	1		T163	1		-	-
all_levels[58]	auto[0]	8	1			T17	1		T103	1		T134	1
all_levels[59]	auto[0]	6	1			T120	1		T34	1		T129	1
all_levels[60]	auto[0]	3	1			T164	1		T165	1		T166	1
all_levels[61]	auto[0]	4	1			T167	1		T168	1		T169	1
all_levels[62]	auto[0]	7	1			T170	1		T171	1		T172	2
all_levels[63]	auto[0]	8	1			T102	1		T136	1		T132	1
all_levels[63]	auto[1]	2	1			T136	2		-	-		-	-
all_levels[64]	auto[0]	72	1			T17	2		T18	1		T19	1
all_levels[64]	auto[1]	25	1			T142	2		T253	5		T254	1