Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_watermark_cg

Group : uart_env_pkg::uart_env_cov::rx_watermark_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.50	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	1	7	87.50

Variables for Group uart_env_pkg::uart_env_cov::rx_watermark_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_watermark_lvl	8	1	7	87.50	100	1	1	0

Summary for Variable cp_watermark_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	1	7	87.50

User Defined Bins for cp_watermark_lvl

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
all_levels[7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	1446	1			T22	18		T101	16		T48	1
all_levels[1]	665	1			T28	8		T26	4		T34	1
all_levels[2]	382	1			T21	17		T13	1		T26	1
all_levels[3]	273	1			T102	10		T103	14		T27	1
all_levels[4]	212	1			T104	8		T24	24		T77	9
all_levels[5]	131	1			T105	3		T73	3		T106	19
all_levels[6]	57	1			T77	6		T107	4		T108	11