Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	89781	1			T1	2		T2	1		T3	2
all_pins[1]	89781	1			T1	2		T2	1		T3	2
all_pins[2]	89781	1			T1	2		T2	1		T3	2
all_pins[3]	89781	1			T1	2		T2	1		T3	2
all_pins[4]	89781	1			T1	2		T2	1		T3	2
all_pins[5]	89781	1			T1	2		T2	1		T3	2
all_pins[6]	89781	1			T1	2		T2	1		T3	2
all_pins[7]	89781	1			T1	2		T2	1		T3	2
all_pins[8]	89781	1			T1	2		T2	1		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	768681	1			T1	18		T2	8		T3	18
values[0x1]	39348	1			T2	1		T8	10		T15	1
transitions[0x0=>0x1]	31032	1			T2	1		T8	9		T15	1
transitions[0x1=>0x0]	30831	1			T8	9		T11	14		T12	30

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	70479	1			T1	2		T3	2		T4	2
all_pins[0]	values[0x1]	19302	1			T2	1		T8	7		T15	1
all_pins[0]	transitions[0x0=>0x1]	18829	1			T2	1		T8	7		T15	1
all_pins[0]	transitions[0x1=>0x0]	1062	1			T28	8		T22	18		T26	1
all_pins[1]	values[0x0]	88246	1			T1	2		T2	1		T3	2
all_pins[1]	values[0x1]	1535	1			T28	8		T13	1		T22	18
all_pins[1]	transitions[0x0=>0x1]	1450	1			T28	8		T22	18		T26	5
all_pins[1]	transitions[0x1=>0x0]	1978	1			T11	4		T12	2		T28	1
all_pins[2]	values[0x0]	87718	1			T1	2		T2	1		T3	2
all_pins[2]	values[0x1]	2063	1			T11	4		T12	2		T28	1
all_pins[2]	transitions[0x0=>0x1]	2015	1			T11	4		T12	2		T28	1
all_pins[2]	transitions[0x1=>0x0]	183	1			T20	2		T19	2		T24	1
all_pins[3]	values[0x0]	89550	1			T1	2		T2	1		T3	2
all_pins[3]	values[0x1]	231	1			T20	2		T19	2		T46	1
all_pins[3]	transitions[0x0=>0x1]	206	1			T20	2		T19	2		T46	1
all_pins[3]	transitions[0x1=>0x0]	279	1			T21	4		T24	1		T76	1
all_pins[4]	values[0x0]	89477	1			T1	2		T2	1		T3	2
all_pins[4]	values[0x1]	304	1			T21	4		T24	1		T76	1
all_pins[4]	transitions[0x0=>0x1]	258	1			T21	4		T24	1		T76	1
all_pins[4]	transitions[0x1=>0x0]	141	1			T76	1		T77	3		T38	2
all_pins[5]	values[0x0]	89594	1			T1	2		T2	1		T3	2
all_pins[5]	values[0x1]	187	1			T76	1		T77	4		T255	1
all_pins[5]	transitions[0x0=>0x1]	143	1			T76	1		T77	4		T255	1
all_pins[5]	transitions[0x1=>0x0]	754	1			T8	1		T12	1		T28	1
all_pins[6]	values[0x0]	88983	1			T1	2		T2	1		T3	2
all_pins[6]	values[0x1]	798	1			T8	1		T12	1		T28	1
all_pins[6]	transitions[0x0=>0x1]	759	1			T8	1		T12	1		T28	1
all_pins[6]	transitions[0x1=>0x0]	228	1			T21	4		T20	5		T102	1
all_pins[7]	values[0x0]	89514	1			T1	2		T2	1		T3	2
all_pins[7]	values[0x1]	267	1			T21	4		T20	5		T102	1
all_pins[7]	transitions[0x0=>0x1]	159	1			T20	4		T19	3		T123	1
all_pins[7]	transitions[0x1=>0x0]	14553	1			T8	2		T11	10		T12	2
all_pins[8]	values[0x0]	75120	1			T1	2		T2	1		T3	2
all_pins[8]	values[0x1]	14661	1			T8	2		T11	10		T12	2
all_pins[8]	transitions[0x0=>0x1]	7213	1			T8	1		T11	9		T28	2
all_pins[8]	transitions[0x1=>0x0]	11653	1			T8	6		T12	25		T45	3