Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	6679932	1			T8	76		T11	16		T12	13
all_levels[1]	1631152	1			T8	8		T11	2		T12	3
all_levels[2]	373927	1			T8	2		T12	1		T45	3
all_levels[3]	183088	1			T8	2		T12	2		T28	8
all_levels[4]	243624	1			T45	2		T28	3		T23	605
all_levels[5]	295037	1			T12	3		T45	3		T23	584
all_levels[6]	179478	1			T23	316		T20	2		T43	1
all_levels[7]	228237	1			T8	2		T23	603		T20	2
all_levels[8]	244184	1			T8	4		T13	1		T23	584
all_levels[9]	197805	1			T8	3		T23	310		T20	2
all_levels[10]	164725	1			T8	16		T45	4		T13	1
all_levels[11]	176849	1			T28	1		T23	604		T43	1
all_levels[12]	166933	1			T8	2		T45	1		T23	331
all_levels[13]	165834	1			T45	4		T23	285		T20	1
all_levels[14]	196277	1			T8	6		T11	7		T45	2
all_levels[15]	501236	1			T11	32		T23	601		T102	1
all_levels[16]	294335	1			T11	2		T28	2		T23	603
all_levels[17]	164460	1			T11	1		T23	601		T18	30
all_levels[18]	152880	1			T11	1		T23	791		T102	4
all_levels[19]	283078	1			T11	1		T13	2		T23	892
all_levels[20]	159050	1			T11	2		T23	598		T20	1
all_levels[21]	159841	1			T23	593		T26	1		T48	2
all_levels[22]	158440	1			T11	1		T28	1		T23	601
all_levels[23]	203540	1			T11	4		T23	539		T26	4
all_levels[24]	211937	1			T11	1		T23	250		T20	1
all_levels[25]	313770	1			T11	5		T28	3		T23	414
all_levels[26]	157390	1			T11	1		T23	602		T123	2
all_levels[27]	161969	1			T23	381		T46	2		T34	2
all_levels[28]	147685	1			T11	1		T23	211		T123	1
all_levels[29]	318238	1			T13	8		T102	4		T46	2
all_levels[30]	379511	1			T11	1		T98	2		T34	2
all_levels[31]	440860	1			T26	2		T49	3		T98	3
all_levels[32]	11662275	1			T11	11		T12	6		T13	10

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26993940

1

T8

120

T11

89

T12

27

auto[1]

3637

1

T8

1

T12

1

T21

36

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	6677815	1			T8	76		T11	16		T12	13
all_levels[0]	auto[1]	2117	1			T21	21		T13	2		T20	1
all_levels[1]	auto[0]	1630926	1			T8	8		T11	2		T12	2
all_levels[1]	auto[1]	226	1			T12	1		T21	15		T103	1
all_levels[2]	auto[0]	373903	1			T8	2		T12	1		T45	3
all_levels[2]	auto[1]	24	1			T95	1		T122	1		T314	1
all_levels[3]	auto[0]	183028	1			T8	2		T12	2		T28	8
all_levels[3]	auto[1]	60	1			T100	8		T121	1		T293	1
all_levels[4]	auto[0]	243596	1			T45	2		T28	3		T23	605
all_levels[4]	auto[1]	28	1			T301	3		T404	1		T405	1
all_levels[5]	auto[0]	295010	1			T12	3		T45	3		T23	584
all_levels[5]	auto[1]	27	1			T406	1		T407	1		T176	3
all_levels[6]	auto[0]	179448	1			T23	316		T20	2		T43	1
all_levels[6]	auto[1]	30	1			T140	1		T330	1		T393	1
all_levels[7]	auto[0]	228146	1			T8	2		T23	603		T20	2
all_levels[7]	auto[1]	91	1			T37	2		T255	18		T263	1
all_levels[8]	auto[0]	244169	1			T8	4		T13	1		T23	584
all_levels[8]	auto[1]	15	1			T364	1		T163	1		T393	3
all_levels[9]	auto[0]	197772	1			T8	3		T23	310		T20	2
all_levels[9]	auto[1]	33	1			T408	3		T341	1		T176	1
all_levels[10]	auto[0]	164695	1			T8	16		T45	4		T13	1
all_levels[10]	auto[1]	30	1			T110	1		T326	1		T235	1
all_levels[11]	auto[0]	176829	1			T28	1		T23	604		T43	1
all_levels[11]	auto[1]	20	1			T325	1		T409	1		T410	1
all_levels[12]	auto[0]	166918	1			T8	2		T45	1		T23	331
all_levels[12]	auto[1]	15	1			T101	2		T170	1		T239	1
all_levels[13]	auto[0]	165799	1			T45	4		T23	285		T20	1
all_levels[13]	auto[1]	35	1			T138	1		T411	1		T412	1
all_levels[14]	auto[0]	196255	1			T8	5		T11	7		T45	2
all_levels[14]	auto[1]	22	1			T8	1		T18	2		T172	3
all_levels[15]	auto[0]	501124	1			T11	32		T23	601		T102	1
all_levels[15]	auto[1]	112	1			T76	20		T351	1		T413	1
all_levels[16]	auto[0]	294316	1			T11	2		T28	2		T23	603
all_levels[16]	auto[1]	19	1			T43	1		T128	1		T257	1
all_levels[17]	auto[0]	164447	1			T11	1		T23	601		T18	29
all_levels[17]	auto[1]	13	1			T18	1		T414	1		T415	1
all_levels[18]	auto[0]	152855	1			T11	1		T23	791		T102	4
all_levels[18]	auto[1]	25	1			T416	1		T417	1		T418	1
all_levels[19]	auto[0]	283063	1			T11	1		T13	1		T23	892
all_levels[19]	auto[1]	15	1			T13	1		T419	3		T420	1
all_levels[20]	auto[0]	159034	1			T11	2		T23	598		T20	1
all_levels[20]	auto[1]	16	1			T133	1		T87	1		T380	1
all_levels[21]	auto[0]	159820	1			T23	593		T26	1		T48	2
all_levels[21]	auto[1]	21	1			T421	1		T176	1		T422	2
all_levels[22]	auto[0]	158414	1			T11	1		T28	1		T23	601
all_levels[22]	auto[1]	26	1			T152	10		T423	2		T164	2
all_levels[23]	auto[0]	203527	1			T11	4		T23	539		T26	4
all_levels[23]	auto[1]	13	1			T103	4		T256	1		T345	1
all_levels[24]	auto[0]	211920	1			T11	1		T23	250		T20	1
all_levels[24]	auto[1]	17	1			T424	1		T198	4		T425	1
all_levels[25]	auto[0]	313756	1			T11	5		T28	3		T23	414
all_levels[25]	auto[1]	14	1			T46	1		T426	2		T147	1
all_levels[26]	auto[0]	157368	1			T11	1		T23	602		T123	2
all_levels[26]	auto[1]	22	1			T98	1		T127	2		T301	1
all_levels[27]	auto[0]	161959	1			T23	381		T46	2		T34	2
all_levels[27]	auto[1]	10	1			T142	1		T424	2		T145	1
all_levels[28]	auto[0]	147669	1			T11	1		T23	211		T123	1
all_levels[28]	auto[1]	16	1			T99	2		T127	1		T427	1
all_levels[29]	auto[0]	318222	1			T13	7		T102	4		T46	2
all_levels[29]	auto[1]	16	1			T13	1		T48	1		T262	1
all_levels[30]	auto[0]	379496	1			T11	1		T98	2		T34	2
all_levels[30]	auto[1]	15	1			T172	1		T428	1		T429	1
all_levels[31]	auto[0]	440850	1			T26	2		T49	3		T98	3
all_levels[31]	auto[1]	10	1			T364	1		T136	1		T430	1
all_levels[32]	auto[0]	11661791	1			T11	11		T12	6		T13	9
all_levels[32]	auto[1]	484	1			T13	1		T26	1		T18	2