Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	604	1			T20	7		T38	14		T73	7
all_values[1]	604	1			T20	7		T38	14		T73	7
all_values[2]	604	1			T20	7		T38	14		T73	7
all_values[3]	604	1			T20	7		T38	14		T73	7
all_values[4]	604	1			T20	7		T38	14		T73	7
all_values[5]	604	1			T20	7		T38	14		T73	7
all_values[6]	604	1			T20	7		T38	14		T73	7
all_values[7]	604	1			T20	7		T38	14		T73	7
all_values[8]	604	1			T20	7		T38	14		T73	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2983

1

T20

34

T38

78

T73

38

auto[1]

2453

1

T20

29

T38

48

T73

25

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1763

1

T20

19

T38

30

T73

24

auto[1]

3673

1

T20

44

T38

96

T73

39

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3218

1

T20

35

T38

66

T73

41

auto[1]

2218

1

T20

28

T38

60

T73

22

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	183	1			T20	2		T38	5		T73	2
all_values[0]	auto[0]	auto[1]	auto[1]	170	1			T20	1		T38	4		T73	3
all_values[0]	auto[1]	auto[0]	auto[1]	132	1			T20	3		T38	4		T74	2
all_values[0]	auto[1]	auto[1]	auto[1]	119	1			T20	1		T38	1		T73	2
all_values[1]	auto[0]	auto[0]	auto[0]	200	1			T20	2		T38	5		T73	3
all_values[1]	auto[0]	auto[1]	auto[0]	152	1			T20	5		T38	5		T73	1
all_values[1]	auto[1]	auto[0]	auto[1]	140	1			T38	2		T73	2		T109	2
all_values[1]	auto[1]	auto[1]	auto[1]	112	1			T38	2		T73	1		T74	1
all_values[2]	auto[0]	auto[0]	auto[0]	138	1			T38	3		T73	5		T109	1
all_values[2]	auto[0]	auto[0]	auto[1]	57	1			T20	1		T38	3		T74	1
all_values[2]	auto[0]	auto[1]	auto[0]	98	1			T38	2		T109	4		T110	3
all_values[2]	auto[0]	auto[1]	auto[1]	57	1			T20	1		T111	1		T110	1
all_values[2]	auto[1]	auto[0]	auto[1]	139	1			T20	4		T38	5		T73	1
all_values[2]	auto[1]	auto[1]	auto[1]	115	1			T20	1		T38	1		T73	1
all_values[3]	auto[0]	auto[0]	auto[0]	151	1			T20	2		T38	4		T73	2
all_values[3]	auto[0]	auto[0]	auto[1]	54	1			T38	1		T73	2		T109	1
all_values[3]	auto[0]	auto[1]	auto[0]	103	1			T20	1		T38	1		T73	1
all_values[3]	auto[0]	auto[1]	auto[1]	63	1			T20	1		T38	2		T74	1
all_values[3]	auto[1]	auto[0]	auto[1]	134	1			T20	3		T38	4		T73	1
all_values[3]	auto[1]	auto[1]	auto[1]	99	1			T38	2		T73	1		T74	1
all_values[4]	auto[0]	auto[0]	auto[0]	129	1			T20	1		T109	2		T112	4
all_values[4]	auto[0]	auto[0]	auto[1]	56	1			T20	1		T38	2		T73	1
all_values[4]	auto[0]	auto[1]	auto[0]	116	1			T20	3		T38	1		T73	3
all_values[4]	auto[0]	auto[1]	auto[1]	51	1			T38	1		T74	1		T110	1
all_values[4]	auto[1]	auto[0]	auto[1]	131	1			T20	2		T38	4		T73	3
all_values[4]	auto[1]	auto[1]	auto[1]	121	1			T38	6		T74	2		T109	1
all_values[5]	auto[0]	auto[0]	auto[0]	130	1			T38	2		T73	1		T74	1
all_values[5]	auto[0]	auto[0]	auto[1]	80	1			T20	2		T38	3		T73	1
all_values[5]	auto[0]	auto[1]	auto[0]	79	1			T20	2		T38	1		T73	1
all_values[5]	auto[0]	auto[1]	auto[1]	59	1			T109	1		T110	1		T113	2
all_values[5]	auto[1]	auto[0]	auto[1]	147	1			T20	2		T38	5		T73	1
all_values[5]	auto[1]	auto[1]	auto[1]	109	1			T20	1		T38	3		T73	3
all_values[6]	auto[0]	auto[0]	auto[0]	137	1			T20	1		T38	3		T73	4
all_values[6]	auto[0]	auto[0]	auto[1]	50	1			T20	1		T38	2		T111	2
all_values[6]	auto[0]	auto[1]	auto[0]	106	1			T20	2		T73	2		T74	2
all_values[6]	auto[0]	auto[1]	auto[1]	70	1			T38	1		T110	1		T113	1
all_values[6]	auto[1]	auto[0]	auto[1]	124	1			T20	2		T38	5		T73	1
all_values[6]	auto[1]	auto[1]	auto[1]	117	1			T20	1		T38	3		T74	1
all_values[7]	auto[0]	auto[0]	auto[0]	136	1			T38	1		T74	1		T109	1
all_values[7]	auto[0]	auto[0]	auto[1]	59	1			T38	2		T73	2		T111	3
all_values[7]	auto[0]	auto[1]	auto[0]	88	1			T38	2		T73	1		T74	1
all_values[7]	auto[0]	auto[1]	auto[1]	68	1			T20	2		T38	1		T109	1
all_values[7]	auto[1]	auto[0]	auto[1]	144	1			T20	2		T38	6		T73	2
all_values[7]	auto[1]	auto[1]	auto[1]	109	1			T20	3		T38	2		T73	2
all_values[8]	auto[0]	auto[0]	auto[1]	207	1			T20	3		T38	5		T73	4
all_values[8]	auto[0]	auto[1]	auto[1]	171	1			T20	1		T38	4		T73	2
all_values[8]	auto[1]	auto[0]	auto[1]	125	1			T38	2		T74	1		T109	2
all_values[8]	auto[1]	auto[1]	auto[1]	101	1			T20	3		T38	3		T73	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal