Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	60406813	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

13448972

1

T1

8

T2

12

T3

25

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	72699576	1			T1	606		T2	101		T3	569
values[0x0]	561273	1			T1	5		T2	9		T3	34
values[0x1]	594936	1			T1	8		T2	6		T3	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	41828361	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

32027424

1

T1

220

T2

39

T3

216

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	252921	1			T3	2		T4	23		T7	2
valid_sources[0x01]	324857	1			T1	9		T3	4		T4	19
valid_sources[0x02]	261132	1			T1	1		T3	6		T4	17
valid_sources[0x03]	376814	1			T1	4		T3	1		T4	6
valid_sources[0x04]	302174	1			T4	44		T7	4		T9	4
valid_sources[0x05]	270136	1			T3	1		T4	16		T7	3
valid_sources[0x06]	253265	1			T1	1		T2	1		T3	3
valid_sources[0x07]	256885	1			T3	5		T4	16		T7	2
valid_sources[0x08]	295178	1			T1	2		T3	4		T4	44
valid_sources[0x09]	260371	1			T1	6		T3	1		T4	18
valid_sources[0x0a]	263908	1			T3	3		T4	5		T7	1
valid_sources[0x0b]	404922	1			T1	4		T2	3		T3	3
valid_sources[0x0c]	314115	1			T1	1		T4	13		T7	5
valid_sources[0x0d]	298726	1			T3	5		T4	15		T7	2
valid_sources[0x0e]	271780	1			T1	1		T3	2		T4	36
valid_sources[0x0f]	260142	1			T1	4		T3	4		T4	14
valid_sources[0x10]	282034	1			T1	3		T3	4		T4	8
valid_sources[0x11]	340940	1			T1	1		T3	3		T4	9
valid_sources[0x12]	250468	1			T1	1		T3	4		T4	14
valid_sources[0x13]	379061	1			T1	4		T2	5		T3	1
valid_sources[0x14]	294627	1			T1	1		T2	7		T3	1
valid_sources[0x15]	282394	1			T1	8		T3	3		T4	27
valid_sources[0x16]	252030	1			T1	7		T3	3		T4	25
valid_sources[0x17]	310997	1			T4	29		T7	4		T9	1
valid_sources[0x18]	303585	1			T1	4		T3	7		T4	21
valid_sources[0x19]	256185	1			T1	3		T2	6		T3	7
valid_sources[0x1a]	270947	1			T1	2		T3	5		T4	29
valid_sources[0x1b]	250400	1			T1	1		T3	1		T4	33
valid_sources[0x1c]	262435	1			T1	5		T3	1		T4	31
valid_sources[0x1d]	334190	1			T3	1		T4	27		T7	2
valid_sources[0x1e]	279442	1			T1	1		T3	1		T4	15
valid_sources[0x1f]	330101	1			T1	5		T2	5		T3	2
valid_sources[0x20]	249929	1			T1	2		T3	1		T4	16
valid_sources[0x21]	261609	1			T1	2		T3	1		T4	12
valid_sources[0x22]	260979	1			T1	2		T3	3		T4	24
valid_sources[0x23]	275439	1			T4	8		T7	5		T10	7
valid_sources[0x24]	299331	1			T1	4		T3	4		T4	15
valid_sources[0x25]	325041	1			T1	1		T3	3		T4	21
valid_sources[0x26]	281860	1			T1	1		T3	4		T4	25
valid_sources[0x27]	295892	1			T1	3		T2	2		T3	6
valid_sources[0x28]	263172	1			T1	8		T3	2		T4	7
valid_sources[0x29]	294334	1			T1	8		T4	32		T7	2
valid_sources[0x2a]	274189	1			T3	1		T4	18		T7	1
valid_sources[0x2b]	245619	1			T3	2		T4	17		T7	1
valid_sources[0x2c]	266663	1			T1	4		T3	1		T4	20
valid_sources[0x2d]	263941	1			T3	2		T4	26		T7	4
valid_sources[0x2e]	298288	1			T1	9		T4	22		T7	4
valid_sources[0x2f]	274559	1			T1	1		T4	10		T7	4
valid_sources[0x30]	393980	1			T1	1		T3	2		T4	19
valid_sources[0x31]	298267	1			T1	4		T3	3		T4	16
valid_sources[0x32]	278136	1			T3	4		T4	15		T6	1
valid_sources[0x33]	249845	1			T1	5		T2	4		T3	1
valid_sources[0x34]	339422	1			T1	1		T4	13		T7	1
valid_sources[0x35]	246491	1			T1	3		T3	2		T4	39
valid_sources[0x36]	252811	1			T1	3		T3	5		T4	6
valid_sources[0x37]	265819	1			T3	7		T4	25		T7	2
valid_sources[0x38]	276367	1			T1	7		T3	3		T4	17
valid_sources[0x39]	268461	1			T1	4		T4	18		T7	10
valid_sources[0x3a]	368405	1			T1	2		T3	4		T4	39
valid_sources[0x3b]	268905	1			T1	2		T3	3		T4	19
valid_sources[0x3c]	251635	1			T1	3		T4	34		T9	1
valid_sources[0x3d]	266369	1			T3	4		T4	46		T9	14
valid_sources[0x3e]	270943	1			T1	5		T2	1		T3	2
valid_sources[0x3f]	262331	1			T1	7		T3	3		T4	6
valid_sources[0x40]	268184	1			T1	3		T3	2		T4	22
valid_sources[0x41]	257893	1			T3	1		T4	15		T7	3
valid_sources[0x42]	259311	1			T1	8		T2	1		T3	3
valid_sources[0x43]	273152	1			T1	8		T3	4		T4	27
valid_sources[0x44]	405246	1			T3	1		T4	33		T7	4
valid_sources[0x45]	274111	1			T1	1		T3	2		T4	27
valid_sources[0x46]	263123	1			T1	1		T3	1		T4	17
valid_sources[0x47]	271346	1			T1	1		T4	13		T9	2
valid_sources[0x48]	258801	1			T1	2		T3	3		T4	26
valid_sources[0x49]	245905	1			T1	4		T4	21		T6	1
valid_sources[0x4a]	258342	1			T1	3		T3	2		T4	14
valid_sources[0x4b]	275217	1			T1	2		T3	3		T4	24
valid_sources[0x4c]	272724	1			T1	1		T4	5		T6	1
valid_sources[0x4d]	286315	1			T3	1		T4	27		T7	6
valid_sources[0x4e]	292370	1			T1	2		T2	2		T3	3
valid_sources[0x4f]	272401	1			T1	5		T3	6		T4	10
valid_sources[0x50]	257314	1			T1	5		T3	7		T4	28
valid_sources[0x51]	328194	1			T1	1		T3	1		T4	12
valid_sources[0x52]	432097	1			T3	2		T4	9		T5	33
valid_sources[0x53]	258594	1			T1	2		T3	3		T4	29
valid_sources[0x54]	278257	1			T3	1		T4	4		T7	3
valid_sources[0x55]	257679	1			T1	1		T2	1		T3	3
valid_sources[0x56]	303469	1			T3	3		T4	11		T7	1
valid_sources[0x57]	265670	1			T1	6		T3	3		T4	8
valid_sources[0x58]	262943	1			T1	4		T2	5		T3	2
valid_sources[0x59]	252037	1			T1	4		T3	1		T4	31
valid_sources[0x5a]	279316	1			T1	3		T3	3		T4	23
valid_sources[0x5b]	252728	1			T1	2		T2	4		T3	4
valid_sources[0x5c]	275433	1			T1	2		T4	21		T5	44
valid_sources[0x5d]	289203	1			T1	1		T3	1		T4	22
valid_sources[0x5e]	266276	1			T1	1		T3	2		T4	22
valid_sources[0x5f]	266911	1			T4	15		T7	4		T9	1
valid_sources[0x60]	321286	1			T1	5		T3	1		T4	12
valid_sources[0x61]	305401	1			T1	2		T2	1		T4	15
valid_sources[0x62]	256078	1			T1	6		T3	2		T4	10
valid_sources[0x63]	310689	1			T1	1		T2	4		T3	3
valid_sources[0x64]	328528	1			T4	21		T7	1		T9	8
valid_sources[0x65]	352436	1			T1	1		T4	26		T5	11
valid_sources[0x66]	299301	1			T3	5		T4	24		T7	1
valid_sources[0x67]	275375	1			T1	3		T3	9		T4	15
valid_sources[0x68]	255500	1			T1	2		T4	48		T5	11
valid_sources[0x69]	253982	1			T1	7		T2	2		T3	3
valid_sources[0x6a]	267939	1			T1	2		T3	1		T4	18
valid_sources[0x6b]	285349	1			T3	1		T4	26		T10	8
valid_sources[0x6c]	279401	1			T4	17		T7	3		T9	5
valid_sources[0x6d]	258713	1			T2	9		T3	1		T4	13
valid_sources[0x6e]	254529	1			T1	4		T3	6		T4	21
valid_sources[0x6f]	259057	1			T1	1		T3	3		T4	8
valid_sources[0x70]	283505	1			T1	2		T3	1		T4	10
valid_sources[0x71]	299089	1			T1	2		T3	5		T4	24
valid_sources[0x72]	318709	1			T1	1		T2	2		T3	2
valid_sources[0x73]	342727	1			T1	5		T4	33		T7	3
valid_sources[0x74]	504641	1			T1	4		T3	1		T4	20
valid_sources[0x75]	293955	1			T1	1		T3	3		T4	20
valid_sources[0x76]	250802	1			T1	2		T3	4		T4	6
valid_sources[0x77]	350400	1			T1	2		T3	2		T4	13
valid_sources[0x78]	276815	1			T1	4		T3	5		T4	12
valid_sources[0x79]	305529	1			T1	3		T3	1		T4	19
valid_sources[0x7a]	340742	1			T3	2		T4	20		T6	1
valid_sources[0x7b]	261506	1			T1	1		T3	3		T4	13
valid_sources[0x7c]	293668	1			T1	3		T3	3		T4	12
valid_sources[0x7d]	307014	1			T1	2		T3	6		T4	17
valid_sources[0x7e]	291822	1			T1	4		T2	1		T4	29
valid_sources[0x7f]	347459	1			T1	6		T4	15		T7	2
valid_sources[0x80]	271806	1			T1	5		T2	5		T3	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

12722764

1

T1

5

T2

1

T3

7

values[0x0]

all_enables

biggest_size

387191

1

T1

1

T2

6

T3

14

values[0x1]

all_enables

biggest_size

339017

1

T1

2

T2

5

T3

4