Line Coverage for Module :
uart_rx
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 35 | 1 | 1 | 100.00 |
| ALWAYS | 38 | 11 | 11 | 100.00 |
| ALWAYS | 54 | 26 | 26 | 100.00 |
| ALWAYS | 93 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 102 | 1 | 1 | 100.00 |
33
34 1/1 assign tick_baud = tick_baud_q;
Tests: T1 T2 T3
35 1/1 assign idle = idle_q;
Tests: T1 T2 T3
36
37 always_ff @(posedge clk_i or negedge rst_ni) begin
38 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
39 1/1 sreg_q <= 11'h0;
Tests: T1 T2 T3
40 1/1 bit_cnt_q <= 4'h0;
Tests: T1 T2 T3
41 1/1 baud_div_q <= 4'h0;
Tests: T1 T2 T3
42 1/1 tick_baud_q <= 1'b0;
Tests: T1 T2 T3
43 1/1 idle_q <= 1'b1;
Tests: T1 T2 T3
44 end else begin
45 1/1 sreg_q <= sreg_d;
Tests: T1 T2 T3
46 1/1 bit_cnt_q <= bit_cnt_d;
Tests: T1 T2 T3
47 1/1 baud_div_q <= baud_div_d;
Tests: T1 T2 T3
48 1/1 tick_baud_q <= tick_baud_d;
Tests: T1 T2 T3
49 1/1 idle_q <= idle_d;
Tests: T1 T2 T3
50 end
51 end
52
53 always_comb begin
54 1/1 if (!rx_enable) begin
Tests: T1 T2 T3
55 1/1 sreg_d = 11'h0;
Tests: T1 T2 T3
56 1/1 bit_cnt_d = 4'h0;
Tests: T1 T2 T3
57 1/1 baud_div_d = 4'h0;
Tests: T1 T2 T3
58 1/1 tick_baud_d = 1'b0;
Tests: T1 T2 T3
59 1/1 idle_d = 1'b1;
Tests: T1 T2 T3
60 end else begin
61 1/1 tick_baud_d = 1'b0;
Tests: T1 T2 T3
62 1/1 sreg_d = sreg_q;
Tests: T1 T2 T3
63 1/1 bit_cnt_d = bit_cnt_q;
Tests: T1 T2 T3
64 1/1 baud_div_d = baud_div_q;
Tests: T1 T2 T3
65 1/1 idle_d = idle_q;
Tests: T1 T2 T3
66 1/1 if (tick_baud_x16) begin
Tests: T1 T2 T3
67 1/1 {tick_baud_d, baud_div_d} = {1'b0,baud_div_q} + 5'h1;
Tests: T1 T2 T3
68 end
MISSING_ELSE
69
70 1/1 if (idle_q && !rx) begin
Tests: T1 T2 T3
71 // start of char, sample in the middle of the bit time
72 1/1 baud_div_d = 4'd8;
Tests: T1 T2 T3
73 1/1 tick_baud_d = 1'b0;
Tests: T1 T2 T3
74 1/1 bit_cnt_d = (parity_enable ? 4'd11 : 4'd10);
Tests: T1 T2 T3
75 1/1 sreg_d = 11'h0;
Tests: T1 T2 T3
76 1/1 idle_d = 1'b0;
Tests: T1 T2 T3
77 1/1 end else if (!idle_q && tick_baud_q) begin
Tests: T1 T2 T3
78 1/1 if ((bit_cnt_q == (parity_enable ? 4'd11 : 4'd10)) && rx) begin
Tests: T1 T2 T3
79 // must have been a glitch on the input, start bit is not set
80 // in the middle of the bit time, abort
81 1/1 idle_d = 1'b1;
Tests: T34 T21 T35
82 1/1 bit_cnt_d = 4'h0;
Tests: T34 T21 T35
83 end else begin
84 1/1 sreg_d = {rx, sreg_q[10:1]};
Tests: T1 T2 T3
85 1/1 bit_cnt_d = bit_cnt_q - 4'h1;
Tests: T1 T2 T3
86 1/1 idle_d = (bit_cnt_q == 4'h1);
Tests: T1 T2 T3
87 end
88 end
MISSING_ELSE
89 end
90 end
91
92 always_ff @(posedge clk_i or negedge rst_ni) begin
93 2/2 if (!rst_ni) rx_valid_q <= 1'b0;
Tests: T1 T2 T3 | T1 T2 T3
94 1/1 else rx_valid_q <= tick_baud_q & (bit_cnt_q == 4'h1);
Tests: T1 T2 T3
95
96 end
97
98 1/1 assign rx_valid = rx_valid_q;
Tests: T1 T2 T3
99 1/1 assign rx_data = parity_enable ? sreg_q[8:1] : sreg_q[9:2];
Tests: T1 T2 T3
100 // (rx_parity = sreg_q[9])
101 1/1 assign frame_err = rx_valid_q & ~sreg_q[10];
Tests: T1 T2 T3
102 1/1 assign rx_parity_err = parity_enable & rx_valid_q &
Tests: T1 T2 T3
Cond Coverage for Module :
uart_rx
| Total | Covered | Percent |
|---|
| Conditions | 29 | 29 | 100.00 |
| Logical | 29 | 29 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 70
EXPRESSION (idle_q && ((!rx)))
---1-- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 74
EXPRESSION (parity_enable ? 4'd11 : 4'd10)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T3,T5 |
| 1 | Covered | T2,T3,T4 |
LINE 77
EXPRESSION (((!idle_q)) && tick_baud_q)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 78
EXPRESSION ((bit_cnt_q == (parity_enable ? 4'd11 : 4'd10)) && rx)
-----------------------1---------------------- -2
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T34,T21,T35 |
LINE 78
SUB-EXPRESSION (bit_cnt_q == (parity_enable ? 4'd11 : 4'd10))
-----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 86
EXPRESSION (bit_cnt_q == 4'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 94
EXPRESSION (tick_baud_q & (bit_cnt_q == 4'b1))
-----1----- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 94
SUB-EXPRESSION (bit_cnt_q == 4'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 99
EXPRESSION (parity_enable ? sreg_q[8:1] : sreg_q[9:2])
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T4 |
LINE 101
EXPRESSION (rx_valid_q & ((~sreg_q[10])))
-----1---- -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T17,T18,T28 |
LINE 102
EXPRESSION (parity_enable & rx_valid_q & ((^{sreg_q[9:1], parity_odd})))
------1------ -----2---- ---------------3--------------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T3,T5 |
| 1 | 0 | 1 | Covered | T2,T3,T4 |
| 1 | 1 | 0 | Covered | T2,T3,T4 |
| 1 | 1 | 1 | Covered | T21,T18,T30 |
Branch Coverage for Module :
uart_rx
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
38 |
2 |
2 |
100.00 |
| IF |
54 |
8 |
8 |
100.00 |
| IF |
93 |
2 |
2 |
100.00 |
99 assign rx_data = parity_enable ? sreg_q[8:1] : sreg_q[9:2];
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T4 |
| 0 |
Covered |
T1,T2,T3 |
38 if (!rst_ni) begin
-1-
39 sreg_q <= 11'h0;
==>
40 bit_cnt_q <= 4'h0;
41 baud_div_q <= 4'h0;
42 tick_baud_q <= 1'b0;
43 idle_q <= 1'b1;
44 end else begin
45 sreg_q <= sreg_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
54 if (!rx_enable) begin
-1-
55 sreg_d = 11'h0;
==>
56 bit_cnt_d = 4'h0;
57 baud_div_d = 4'h0;
58 tick_baud_d = 1'b0;
59 idle_d = 1'b1;
60 end else begin
61 tick_baud_d = 1'b0;
62 sreg_d = sreg_q;
63 bit_cnt_d = bit_cnt_q;
64 baud_div_d = baud_div_q;
65 idle_d = idle_q;
66 if (tick_baud_x16) begin
-2-
67 {tick_baud_d, baud_div_d} = {1'b0,baud_div_q} + 5'h1;
==>
68 end
MISSING_ELSE
==>
69
70 if (idle_q && !rx) begin
-3-
71 // start of char, sample in the middle of the bit time
72 baud_div_d = 4'd8;
73 tick_baud_d = 1'b0;
74 bit_cnt_d = (parity_enable ? 4'd11 : 4'd10);
-4-
==>
==>
75 sreg_d = 11'h0;
76 idle_d = 1'b0;
77 end else if (!idle_q && tick_baud_q) begin
-5-
78 if ((bit_cnt_q == (parity_enable ? 4'd11 : 4'd10)) && rx) begin
-6-
79 // must have been a glitch on the input, start bit is not set
80 // in the middle of the bit time, abort
81 idle_d = 1'b1;
==>
82 bit_cnt_d = 4'h0;
83 end else begin
84 sreg_d = {rx, sreg_q[10:1]};
==>
85 bit_cnt_d = bit_cnt_q - 4'h1;
86 idle_d = (bit_cnt_q == 4'h1);
87 end
88 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
| 1 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
- |
1 |
1 |
- |
- |
Covered |
T2,T3,T4 |
| 0 |
- |
1 |
0 |
- |
- |
Covered |
T1,T3,T5 |
| 0 |
- |
0 |
- |
1 |
1 |
Covered |
T34,T21,T35 |
| 0 |
- |
0 |
- |
1 |
0 |
Covered |
T1,T2,T3 |
| 0 |
- |
0 |
- |
0 |
- |
Covered |
T1,T2,T3 |
93 if (!rst_ni) rx_valid_q <= 1'b0;
-1-
==>
94 else rx_valid_q <= tick_baud_q & (bit_cnt_q == 4'h1);
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
