Line Coverage for Module :
uart_reg_top
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 172 | 172 | 100.00 |
| ALWAYS | 68 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 77 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 90 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 718 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 733 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 749 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 765 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 781 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 797 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 813 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 829 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 845 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 861 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 867 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 881 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1274 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1315 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1343 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1371 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1399 | 1 | 1 | 100.00 |
| ALWAYS | 1565 | 14 | 14 | 100.00 |
| CONT_ASSIGN | 1581 | 1 | 1 | 100.00 |
| ALWAYS | 1585 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1602 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1604 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1606 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1608 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1610 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1612 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1614 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1615 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1617 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1619 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1621 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1623 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1625 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1627 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1629 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1631 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1633 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1634 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1636 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1638 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1640 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1642 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1644 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1646 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1648 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1650 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1652 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1653 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1655 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1656 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1658 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1660 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1662 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1664 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1666 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1668 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1670 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1672 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1674 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1675 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1676 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1677 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1679 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1680 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1682 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1684 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1686 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1688 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1689 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1690 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1692 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1694 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1695 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1696 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1698 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1700 | 1 | 1 | 100.00 |
| ALWAYS | 1704 | 14 | 14 | 100.00 |
| ALWAYS | 1722 | 58 | 58 | 100.00 |
| CONT_ASSIGN | 1830 | 0 | 0 | |
| CONT_ASSIGN | 1838 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1839 | 1 | 1 | 100.00 |
67 always_ff @(posedge clk_i or negedge rst_ni) begin
68 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
69 1/1 err_q <= '0;
Tests: T1 T2 T3
70 1/1 end else if (intg_err || reg_we_err) begin
Tests: T1 T2 T3
71 1/1 err_q <= 1'b1;
Tests: T8 T36 T39
72 end
MISSING_ELSE
73 end
74
75 // integrity error output is permanent and should be used for alert generation
76 // register errors are transactional
77 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T1 T2 T3
78
79 // outgoing integrity generation
80 tlul_pkg::tl_d2h_t tl_o_pre;
81 tlul_rsp_intg_gen #(
82 .EnableRspIntgGen(1),
83 .EnableDataIntgGen(1)
84 ) u_rsp_intg_gen (
85 .tl_i(tl_o_pre),
86 .tl_o(tl_o)
87 );
88
89 1/1 assign tl_reg_h2d = tl_i;
Tests: T1 T2 T3
90 1/1 assign tl_o_pre = tl_reg_d2h;
Tests: T1 T2 T3
91
92 tlul_adapter_reg #(
93 .RegAw(AW),
94 .RegDw(DW),
95 .EnableDataIntgGen(0)
96 ) u_reg_if (
97 .clk_i (clk_i),
98 .rst_ni (rst_ni),
99
100 .tl_i (tl_reg_h2d),
101 .tl_o (tl_reg_d2h),
102
103 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
104 .intg_error_o(),
105
106 .we_o (reg_we),
107 .re_o (reg_re),
108 .addr_o (reg_addr),
109 .wdata_o (reg_wdata),
110 .be_o (reg_be),
111 .busy_i (reg_busy),
112 .rdata_i (reg_rdata),
113 .error_i (reg_error)
114 );
115
116 // cdc oversampling signals
117
118 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T1 T2 T3
119 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T10 T31 T32
120
121 // Define SW related signals
122 // Format: <reg>_<field>_{wd|we|qs}
123 // or <reg>_{wd|we|qs} if field == 1 or 0
124 logic intr_state_we;
125 logic intr_state_tx_watermark_qs;
126 logic intr_state_rx_watermark_qs;
127 logic intr_state_tx_done_qs;
128 logic intr_state_tx_done_wd;
129 logic intr_state_rx_overflow_qs;
130 logic intr_state_rx_overflow_wd;
131 logic intr_state_rx_frame_err_qs;
132 logic intr_state_rx_frame_err_wd;
133 logic intr_state_rx_break_err_qs;
134 logic intr_state_rx_break_err_wd;
135 logic intr_state_rx_timeout_qs;
136 logic intr_state_rx_timeout_wd;
137 logic intr_state_rx_parity_err_qs;
138 logic intr_state_rx_parity_err_wd;
139 logic intr_state_tx_empty_qs;
140 logic intr_enable_we;
141 logic intr_enable_tx_watermark_qs;
142 logic intr_enable_tx_watermark_wd;
143 logic intr_enable_rx_watermark_qs;
144 logic intr_enable_rx_watermark_wd;
145 logic intr_enable_tx_done_qs;
146 logic intr_enable_tx_done_wd;
147 logic intr_enable_rx_overflow_qs;
148 logic intr_enable_rx_overflow_wd;
149 logic intr_enable_rx_frame_err_qs;
150 logic intr_enable_rx_frame_err_wd;
151 logic intr_enable_rx_break_err_qs;
152 logic intr_enable_rx_break_err_wd;
153 logic intr_enable_rx_timeout_qs;
154 logic intr_enable_rx_timeout_wd;
155 logic intr_enable_rx_parity_err_qs;
156 logic intr_enable_rx_parity_err_wd;
157 logic intr_enable_tx_empty_qs;
158 logic intr_enable_tx_empty_wd;
159 logic intr_test_we;
160 logic intr_test_tx_watermark_wd;
161 logic intr_test_rx_watermark_wd;
162 logic intr_test_tx_done_wd;
163 logic intr_test_rx_overflow_wd;
164 logic intr_test_rx_frame_err_wd;
165 logic intr_test_rx_break_err_wd;
166 logic intr_test_rx_timeout_wd;
167 logic intr_test_rx_parity_err_wd;
168 logic intr_test_tx_empty_wd;
169 logic alert_test_we;
170 logic alert_test_wd;
171 logic ctrl_we;
172 logic ctrl_tx_qs;
173 logic ctrl_tx_wd;
174 logic ctrl_rx_qs;
175 logic ctrl_rx_wd;
176 logic ctrl_nf_qs;
177 logic ctrl_nf_wd;
178 logic ctrl_slpbk_qs;
179 logic ctrl_slpbk_wd;
180 logic ctrl_llpbk_qs;
181 logic ctrl_llpbk_wd;
182 logic ctrl_parity_en_qs;
183 logic ctrl_parity_en_wd;
184 logic ctrl_parity_odd_qs;
185 logic ctrl_parity_odd_wd;
186 logic [1:0] ctrl_rxblvl_qs;
187 logic [1:0] ctrl_rxblvl_wd;
188 logic [15:0] ctrl_nco_qs;
189 logic [15:0] ctrl_nco_wd;
190 logic status_re;
191 logic status_txfull_qs;
192 logic status_rxfull_qs;
193 logic status_txempty_qs;
194 logic status_txidle_qs;
195 logic status_rxidle_qs;
196 logic status_rxempty_qs;
197 logic rdata_re;
198 logic [7:0] rdata_qs;
199 logic wdata_we;
200 logic [7:0] wdata_wd;
201 logic fifo_ctrl_we;
202 logic fifo_ctrl_rxrst_wd;
203 logic fifo_ctrl_txrst_wd;
204 logic [2:0] fifo_ctrl_rxilvl_qs;
205 logic [2:0] fifo_ctrl_rxilvl_wd;
206 logic [2:0] fifo_ctrl_txilvl_qs;
207 logic [2:0] fifo_ctrl_txilvl_wd;
208 logic fifo_status_re;
209 logic [7:0] fifo_status_txlvl_qs;
210 logic [7:0] fifo_status_rxlvl_qs;
211 logic ovrd_we;
212 logic ovrd_txen_qs;
213 logic ovrd_txen_wd;
214 logic ovrd_txval_qs;
215 logic ovrd_txval_wd;
216 logic val_re;
217 logic [15:0] val_qs;
218 logic timeout_ctrl_we;
219 logic [23:0] timeout_ctrl_val_qs;
220 logic [23:0] timeout_ctrl_val_wd;
221 logic timeout_ctrl_en_qs;
222 logic timeout_ctrl_en_wd;
223
224 // Register instances
225 // R[intr_state]: V(False)
226 // F[tx_watermark]: 0:0
227 prim_subreg #(
228 .DW (1),
229 .SwAccess(prim_subreg_pkg::SwAccessRO),
230 .RESVAL (1'h1),
231 .Mubi (1'b0)
232 ) u_intr_state_tx_watermark (
233 .clk_i (clk_i),
234 .rst_ni (rst_ni),
235
236 // from register interface
237 .we (1'b0),
238 .wd ('0),
239
240 // from internal hardware
241 .de (hw2reg.intr_state.tx_watermark.de),
242 .d (hw2reg.intr_state.tx_watermark.d),
243
244 // to internal hardware
245 .qe (),
246 .q (reg2hw.intr_state.tx_watermark.q),
247 .ds (),
248
249 // to register interface (read)
250 .qs (intr_state_tx_watermark_qs)
251 );
252
253 // F[rx_watermark]: 1:1
254 prim_subreg #(
255 .DW (1),
256 .SwAccess(prim_subreg_pkg::SwAccessRO),
257 .RESVAL (1'h0),
258 .Mubi (1'b0)
259 ) u_intr_state_rx_watermark (
260 .clk_i (clk_i),
261 .rst_ni (rst_ni),
262
263 // from register interface
264 .we (1'b0),
265 .wd ('0),
266
267 // from internal hardware
268 .de (hw2reg.intr_state.rx_watermark.de),
269 .d (hw2reg.intr_state.rx_watermark.d),
270
271 // to internal hardware
272 .qe (),
273 .q (reg2hw.intr_state.rx_watermark.q),
274 .ds (),
275
276 // to register interface (read)
277 .qs (intr_state_rx_watermark_qs)
278 );
279
280 // F[tx_done]: 2:2
281 prim_subreg #(
282 .DW (1),
283 .SwAccess(prim_subreg_pkg::SwAccessW1C),
284 .RESVAL (1'h0),
285 .Mubi (1'b0)
286 ) u_intr_state_tx_done (
287 .clk_i (clk_i),
288 .rst_ni (rst_ni),
289
290 // from register interface
291 .we (intr_state_we),
292 .wd (intr_state_tx_done_wd),
293
294 // from internal hardware
295 .de (hw2reg.intr_state.tx_done.de),
296 .d (hw2reg.intr_state.tx_done.d),
297
298 // to internal hardware
299 .qe (),
300 .q (reg2hw.intr_state.tx_done.q),
301 .ds (),
302
303 // to register interface (read)
304 .qs (intr_state_tx_done_qs)
305 );
306
307 // F[rx_overflow]: 3:3
308 prim_subreg #(
309 .DW (1),
310 .SwAccess(prim_subreg_pkg::SwAccessW1C),
311 .RESVAL (1'h0),
312 .Mubi (1'b0)
313 ) u_intr_state_rx_overflow (
314 .clk_i (clk_i),
315 .rst_ni (rst_ni),
316
317 // from register interface
318 .we (intr_state_we),
319 .wd (intr_state_rx_overflow_wd),
320
321 // from internal hardware
322 .de (hw2reg.intr_state.rx_overflow.de),
323 .d (hw2reg.intr_state.rx_overflow.d),
324
325 // to internal hardware
326 .qe (),
327 .q (reg2hw.intr_state.rx_overflow.q),
328 .ds (),
329
330 // to register interface (read)
331 .qs (intr_state_rx_overflow_qs)
332 );
333
334 // F[rx_frame_err]: 4:4
335 prim_subreg #(
336 .DW (1),
337 .SwAccess(prim_subreg_pkg::SwAccessW1C),
338 .RESVAL (1'h0),
339 .Mubi (1'b0)
340 ) u_intr_state_rx_frame_err (
341 .clk_i (clk_i),
342 .rst_ni (rst_ni),
343
344 // from register interface
345 .we (intr_state_we),
346 .wd (intr_state_rx_frame_err_wd),
347
348 // from internal hardware
349 .de (hw2reg.intr_state.rx_frame_err.de),
350 .d (hw2reg.intr_state.rx_frame_err.d),
351
352 // to internal hardware
353 .qe (),
354 .q (reg2hw.intr_state.rx_frame_err.q),
355 .ds (),
356
357 // to register interface (read)
358 .qs (intr_state_rx_frame_err_qs)
359 );
360
361 // F[rx_break_err]: 5:5
362 prim_subreg #(
363 .DW (1),
364 .SwAccess(prim_subreg_pkg::SwAccessW1C),
365 .RESVAL (1'h0),
366 .Mubi (1'b0)
367 ) u_intr_state_rx_break_err (
368 .clk_i (clk_i),
369 .rst_ni (rst_ni),
370
371 // from register interface
372 .we (intr_state_we),
373 .wd (intr_state_rx_break_err_wd),
374
375 // from internal hardware
376 .de (hw2reg.intr_state.rx_break_err.de),
377 .d (hw2reg.intr_state.rx_break_err.d),
378
379 // to internal hardware
380 .qe (),
381 .q (reg2hw.intr_state.rx_break_err.q),
382 .ds (),
383
384 // to register interface (read)
385 .qs (intr_state_rx_break_err_qs)
386 );
387
388 // F[rx_timeout]: 6:6
389 prim_subreg #(
390 .DW (1),
391 .SwAccess(prim_subreg_pkg::SwAccessW1C),
392 .RESVAL (1'h0),
393 .Mubi (1'b0)
394 ) u_intr_state_rx_timeout (
395 .clk_i (clk_i),
396 .rst_ni (rst_ni),
397
398 // from register interface
399 .we (intr_state_we),
400 .wd (intr_state_rx_timeout_wd),
401
402 // from internal hardware
403 .de (hw2reg.intr_state.rx_timeout.de),
404 .d (hw2reg.intr_state.rx_timeout.d),
405
406 // to internal hardware
407 .qe (),
408 .q (reg2hw.intr_state.rx_timeout.q),
409 .ds (),
410
411 // to register interface (read)
412 .qs (intr_state_rx_timeout_qs)
413 );
414
415 // F[rx_parity_err]: 7:7
416 prim_subreg #(
417 .DW (1),
418 .SwAccess(prim_subreg_pkg::SwAccessW1C),
419 .RESVAL (1'h0),
420 .Mubi (1'b0)
421 ) u_intr_state_rx_parity_err (
422 .clk_i (clk_i),
423 .rst_ni (rst_ni),
424
425 // from register interface
426 .we (intr_state_we),
427 .wd (intr_state_rx_parity_err_wd),
428
429 // from internal hardware
430 .de (hw2reg.intr_state.rx_parity_err.de),
431 .d (hw2reg.intr_state.rx_parity_err.d),
432
433 // to internal hardware
434 .qe (),
435 .q (reg2hw.intr_state.rx_parity_err.q),
436 .ds (),
437
438 // to register interface (read)
439 .qs (intr_state_rx_parity_err_qs)
440 );
441
442 // F[tx_empty]: 8:8
443 prim_subreg #(
444 .DW (1),
445 .SwAccess(prim_subreg_pkg::SwAccessRO),
446 .RESVAL (1'h1),
447 .Mubi (1'b0)
448 ) u_intr_state_tx_empty (
449 .clk_i (clk_i),
450 .rst_ni (rst_ni),
451
452 // from register interface
453 .we (1'b0),
454 .wd ('0),
455
456 // from internal hardware
457 .de (hw2reg.intr_state.tx_empty.de),
458 .d (hw2reg.intr_state.tx_empty.d),
459
460 // to internal hardware
461 .qe (),
462 .q (reg2hw.intr_state.tx_empty.q),
463 .ds (),
464
465 // to register interface (read)
466 .qs (intr_state_tx_empty_qs)
467 );
468
469
470 // R[intr_enable]: V(False)
471 // F[tx_watermark]: 0:0
472 prim_subreg #(
473 .DW (1),
474 .SwAccess(prim_subreg_pkg::SwAccessRW),
475 .RESVAL (1'h0),
476 .Mubi (1'b0)
477 ) u_intr_enable_tx_watermark (
478 .clk_i (clk_i),
479 .rst_ni (rst_ni),
480
481 // from register interface
482 .we (intr_enable_we),
483 .wd (intr_enable_tx_watermark_wd),
484
485 // from internal hardware
486 .de (1'b0),
487 .d ('0),
488
489 // to internal hardware
490 .qe (),
491 .q (reg2hw.intr_enable.tx_watermark.q),
492 .ds (),
493
494 // to register interface (read)
495 .qs (intr_enable_tx_watermark_qs)
496 );
497
498 // F[rx_watermark]: 1:1
499 prim_subreg #(
500 .DW (1),
501 .SwAccess(prim_subreg_pkg::SwAccessRW),
502 .RESVAL (1'h0),
503 .Mubi (1'b0)
504 ) u_intr_enable_rx_watermark (
505 .clk_i (clk_i),
506 .rst_ni (rst_ni),
507
508 // from register interface
509 .we (intr_enable_we),
510 .wd (intr_enable_rx_watermark_wd),
511
512 // from internal hardware
513 .de (1'b0),
514 .d ('0),
515
516 // to internal hardware
517 .qe (),
518 .q (reg2hw.intr_enable.rx_watermark.q),
519 .ds (),
520
521 // to register interface (read)
522 .qs (intr_enable_rx_watermark_qs)
523 );
524
525 // F[tx_done]: 2:2
526 prim_subreg #(
527 .DW (1),
528 .SwAccess(prim_subreg_pkg::SwAccessRW),
529 .RESVAL (1'h0),
530 .Mubi (1'b0)
531 ) u_intr_enable_tx_done (
532 .clk_i (clk_i),
533 .rst_ni (rst_ni),
534
535 // from register interface
536 .we (intr_enable_we),
537 .wd (intr_enable_tx_done_wd),
538
539 // from internal hardware
540 .de (1'b0),
541 .d ('0),
542
543 // to internal hardware
544 .qe (),
545 .q (reg2hw.intr_enable.tx_done.q),
546 .ds (),
547
548 // to register interface (read)
549 .qs (intr_enable_tx_done_qs)
550 );
551
552 // F[rx_overflow]: 3:3
553 prim_subreg #(
554 .DW (1),
555 .SwAccess(prim_subreg_pkg::SwAccessRW),
556 .RESVAL (1'h0),
557 .Mubi (1'b0)
558 ) u_intr_enable_rx_overflow (
559 .clk_i (clk_i),
560 .rst_ni (rst_ni),
561
562 // from register interface
563 .we (intr_enable_we),
564 .wd (intr_enable_rx_overflow_wd),
565
566 // from internal hardware
567 .de (1'b0),
568 .d ('0),
569
570 // to internal hardware
571 .qe (),
572 .q (reg2hw.intr_enable.rx_overflow.q),
573 .ds (),
574
575 // to register interface (read)
576 .qs (intr_enable_rx_overflow_qs)
577 );
578
579 // F[rx_frame_err]: 4:4
580 prim_subreg #(
581 .DW (1),
582 .SwAccess(prim_subreg_pkg::SwAccessRW),
583 .RESVAL (1'h0),
584 .Mubi (1'b0)
585 ) u_intr_enable_rx_frame_err (
586 .clk_i (clk_i),
587 .rst_ni (rst_ni),
588
589 // from register interface
590 .we (intr_enable_we),
591 .wd (intr_enable_rx_frame_err_wd),
592
593 // from internal hardware
594 .de (1'b0),
595 .d ('0),
596
597 // to internal hardware
598 .qe (),
599 .q (reg2hw.intr_enable.rx_frame_err.q),
600 .ds (),
601
602 // to register interface (read)
603 .qs (intr_enable_rx_frame_err_qs)
604 );
605
606 // F[rx_break_err]: 5:5
607 prim_subreg #(
608 .DW (1),
609 .SwAccess(prim_subreg_pkg::SwAccessRW),
610 .RESVAL (1'h0),
611 .Mubi (1'b0)
612 ) u_intr_enable_rx_break_err (
613 .clk_i (clk_i),
614 .rst_ni (rst_ni),
615
616 // from register interface
617 .we (intr_enable_we),
618 .wd (intr_enable_rx_break_err_wd),
619
620 // from internal hardware
621 .de (1'b0),
622 .d ('0),
623
624 // to internal hardware
625 .qe (),
626 .q (reg2hw.intr_enable.rx_break_err.q),
627 .ds (),
628
629 // to register interface (read)
630 .qs (intr_enable_rx_break_err_qs)
631 );
632
633 // F[rx_timeout]: 6:6
634 prim_subreg #(
635 .DW (1),
636 .SwAccess(prim_subreg_pkg::SwAccessRW),
637 .RESVAL (1'h0),
638 .Mubi (1'b0)
639 ) u_intr_enable_rx_timeout (
640 .clk_i (clk_i),
641 .rst_ni (rst_ni),
642
643 // from register interface
644 .we (intr_enable_we),
645 .wd (intr_enable_rx_timeout_wd),
646
647 // from internal hardware
648 .de (1'b0),
649 .d ('0),
650
651 // to internal hardware
652 .qe (),
653 .q (reg2hw.intr_enable.rx_timeout.q),
654 .ds (),
655
656 // to register interface (read)
657 .qs (intr_enable_rx_timeout_qs)
658 );
659
660 // F[rx_parity_err]: 7:7
661 prim_subreg #(
662 .DW (1),
663 .SwAccess(prim_subreg_pkg::SwAccessRW),
664 .RESVAL (1'h0),
665 .Mubi (1'b0)
666 ) u_intr_enable_rx_parity_err (
667 .clk_i (clk_i),
668 .rst_ni (rst_ni),
669
670 // from register interface
671 .we (intr_enable_we),
672 .wd (intr_enable_rx_parity_err_wd),
673
674 // from internal hardware
675 .de (1'b0),
676 .d ('0),
677
678 // to internal hardware
679 .qe (),
680 .q (reg2hw.intr_enable.rx_parity_err.q),
681 .ds (),
682
683 // to register interface (read)
684 .qs (intr_enable_rx_parity_err_qs)
685 );
686
687 // F[tx_empty]: 8:8
688 prim_subreg #(
689 .DW (1),
690 .SwAccess(prim_subreg_pkg::SwAccessRW),
691 .RESVAL (1'h0),
692 .Mubi (1'b0)
693 ) u_intr_enable_tx_empty (
694 .clk_i (clk_i),
695 .rst_ni (rst_ni),
696
697 // from register interface
698 .we (intr_enable_we),
699 .wd (intr_enable_tx_empty_wd),
700
701 // from internal hardware
702 .de (1'b0),
703 .d ('0),
704
705 // to internal hardware
706 .qe (),
707 .q (reg2hw.intr_enable.tx_empty.q),
708 .ds (),
709
710 // to register interface (read)
711 .qs (intr_enable_tx_empty_qs)
712 );
713
714
715 // R[intr_test]: V(True)
716 logic intr_test_qe;
717 logic [8:0] intr_test_flds_we;
718 1/1 assign intr_test_qe = &intr_test_flds_we;
Tests: T10 T31 T32
719 // F[tx_watermark]: 0:0
720 prim_subreg_ext #(
721 .DW (1)
722 ) u_intr_test_tx_watermark (
723 .re (1'b0),
724 .we (intr_test_we),
725 .wd (intr_test_tx_watermark_wd),
726 .d ('0),
727 .qre (),
728 .qe (intr_test_flds_we[0]),
729 .q (reg2hw.intr_test.tx_watermark.q),
730 .ds (),
731 .qs ()
732 );
733 1/1 assign reg2hw.intr_test.tx_watermark.qe = intr_test_qe;
Tests: T10 T31 T32
734
735 // F[rx_watermark]: 1:1
736 prim_subreg_ext #(
737 .DW (1)
738 ) u_intr_test_rx_watermark (
739 .re (1'b0),
740 .we (intr_test_we),
741 .wd (intr_test_rx_watermark_wd),
742 .d ('0),
743 .qre (),
744 .qe (intr_test_flds_we[1]),
745 .q (reg2hw.intr_test.rx_watermark.q),
746 .ds (),
747 .qs ()
748 );
749 1/1 assign reg2hw.intr_test.rx_watermark.qe = intr_test_qe;
Tests: T10 T31 T32
750
751 // F[tx_done]: 2:2
752 prim_subreg_ext #(
753 .DW (1)
754 ) u_intr_test_tx_done (
755 .re (1'b0),
756 .we (intr_test_we),
757 .wd (intr_test_tx_done_wd),
758 .d ('0),
759 .qre (),
760 .qe (intr_test_flds_we[2]),
761 .q (reg2hw.intr_test.tx_done.q),
762 .ds (),
763 .qs ()
764 );
765 1/1 assign reg2hw.intr_test.tx_done.qe = intr_test_qe;
Tests: T10 T31 T32
766
767 // F[rx_overflow]: 3:3
768 prim_subreg_ext #(
769 .DW (1)
770 ) u_intr_test_rx_overflow (
771 .re (1'b0),
772 .we (intr_test_we),
773 .wd (intr_test_rx_overflow_wd),
774 .d ('0),
775 .qre (),
776 .qe (intr_test_flds_we[3]),
777 .q (reg2hw.intr_test.rx_overflow.q),
778 .ds (),
779 .qs ()
780 );
781 1/1 assign reg2hw.intr_test.rx_overflow.qe = intr_test_qe;
Tests: T10 T31 T32
782
783 // F[rx_frame_err]: 4:4
784 prim_subreg_ext #(
785 .DW (1)
786 ) u_intr_test_rx_frame_err (
787 .re (1'b0),
788 .we (intr_test_we),
789 .wd (intr_test_rx_frame_err_wd),
790 .d ('0),
791 .qre (),
792 .qe (intr_test_flds_we[4]),
793 .q (reg2hw.intr_test.rx_frame_err.q),
794 .ds (),
795 .qs ()
796 );
797 1/1 assign reg2hw.intr_test.rx_frame_err.qe = intr_test_qe;
Tests: T10 T31 T32
798
799 // F[rx_break_err]: 5:5
800 prim_subreg_ext #(
801 .DW (1)
802 ) u_intr_test_rx_break_err (
803 .re (1'b0),
804 .we (intr_test_we),
805 .wd (intr_test_rx_break_err_wd),
806 .d ('0),
807 .qre (),
808 .qe (intr_test_flds_we[5]),
809 .q (reg2hw.intr_test.rx_break_err.q),
810 .ds (),
811 .qs ()
812 );
813 1/1 assign reg2hw.intr_test.rx_break_err.qe = intr_test_qe;
Tests: T10 T31 T32
814
815 // F[rx_timeout]: 6:6
816 prim_subreg_ext #(
817 .DW (1)
818 ) u_intr_test_rx_timeout (
819 .re (1'b0),
820 .we (intr_test_we),
821 .wd (intr_test_rx_timeout_wd),
822 .d ('0),
823 .qre (),
824 .qe (intr_test_flds_we[6]),
825 .q (reg2hw.intr_test.rx_timeout.q),
826 .ds (),
827 .qs ()
828 );
829 1/1 assign reg2hw.intr_test.rx_timeout.qe = intr_test_qe;
Tests: T10 T31 T32
830
831 // F[rx_parity_err]: 7:7
832 prim_subreg_ext #(
833 .DW (1)
834 ) u_intr_test_rx_parity_err (
835 .re (1'b0),
836 .we (intr_test_we),
837 .wd (intr_test_rx_parity_err_wd),
838 .d ('0),
839 .qre (),
840 .qe (intr_test_flds_we[7]),
841 .q (reg2hw.intr_test.rx_parity_err.q),
842 .ds (),
843 .qs ()
844 );
845 1/1 assign reg2hw.intr_test.rx_parity_err.qe = intr_test_qe;
Tests: T10 T31 T32
846
847 // F[tx_empty]: 8:8
848 prim_subreg_ext #(
849 .DW (1)
850 ) u_intr_test_tx_empty (
851 .re (1'b0),
852 .we (intr_test_we),
853 .wd (intr_test_tx_empty_wd),
854 .d ('0),
855 .qre (),
856 .qe (intr_test_flds_we[8]),
857 .q (reg2hw.intr_test.tx_empty.q),
858 .ds (),
859 .qs ()
860 );
861 1/1 assign reg2hw.intr_test.tx_empty.qe = intr_test_qe;
Tests: T10 T31 T32
862
863
864 // R[alert_test]: V(True)
865 logic alert_test_qe;
866 logic [0:0] alert_test_flds_we;
867 1/1 assign alert_test_qe = &alert_test_flds_we;
Tests: T6 T10 T37
868 prim_subreg_ext #(
869 .DW (1)
870 ) u_alert_test (
871 .re (1'b0),
872 .we (alert_test_we),
873 .wd (alert_test_wd),
874 .d ('0),
875 .qre (),
876 .qe (alert_test_flds_we[0]),
877 .q (reg2hw.alert_test.q),
878 .ds (),
879 .qs ()
880 );
881 1/1 assign reg2hw.alert_test.qe = alert_test_qe;
Tests: T6 T10 T37
882
883
884 // R[ctrl]: V(False)
885 // F[tx]: 0:0
886 prim_subreg #(
887 .DW (1),
888 .SwAccess(prim_subreg_pkg::SwAccessRW),
889 .RESVAL (1'h0),
890 .Mubi (1'b0)
891 ) u_ctrl_tx (
892 .clk_i (clk_i),
893 .rst_ni (rst_ni),
894
895 // from register interface
896 .we (ctrl_we),
897 .wd (ctrl_tx_wd),
898
899 // from internal hardware
900 .de (1'b0),
901 .d ('0),
902
903 // to internal hardware
904 .qe (),
905 .q (reg2hw.ctrl.tx.q),
906 .ds (),
907
908 // to register interface (read)
909 .qs (ctrl_tx_qs)
910 );
911
912 // F[rx]: 1:1
913 prim_subreg #(
914 .DW (1),
915 .SwAccess(prim_subreg_pkg::SwAccessRW),
916 .RESVAL (1'h0),
917 .Mubi (1'b0)
918 ) u_ctrl_rx (
919 .clk_i (clk_i),
920 .rst_ni (rst_ni),
921
922 // from register interface
923 .we (ctrl_we),
924 .wd (ctrl_rx_wd),
925
926 // from internal hardware
927 .de (1'b0),
928 .d ('0),
929
930 // to internal hardware
931 .qe (),
932 .q (reg2hw.ctrl.rx.q),
933 .ds (),
934
935 // to register interface (read)
936 .qs (ctrl_rx_qs)
937 );
938
939 // F[nf]: 2:2
940 prim_subreg #(
941 .DW (1),
942 .SwAccess(prim_subreg_pkg::SwAccessRW),
943 .RESVAL (1'h0),
944 .Mubi (1'b0)
945 ) u_ctrl_nf (
946 .clk_i (clk_i),
947 .rst_ni (rst_ni),
948
949 // from register interface
950 .we (ctrl_we),
951 .wd (ctrl_nf_wd),
952
953 // from internal hardware
954 .de (1'b0),
955 .d ('0),
956
957 // to internal hardware
958 .qe (),
959 .q (reg2hw.ctrl.nf.q),
960 .ds (),
961
962 // to register interface (read)
963 .qs (ctrl_nf_qs)
964 );
965
966 // F[slpbk]: 4:4
967 prim_subreg #(
968 .DW (1),
969 .SwAccess(prim_subreg_pkg::SwAccessRW),
970 .RESVAL (1'h0),
971 .Mubi (1'b0)
972 ) u_ctrl_slpbk (
973 .clk_i (clk_i),
974 .rst_ni (rst_ni),
975
976 // from register interface
977 .we (ctrl_we),
978 .wd (ctrl_slpbk_wd),
979
980 // from internal hardware
981 .de (1'b0),
982 .d ('0),
983
984 // to internal hardware
985 .qe (),
986 .q (reg2hw.ctrl.slpbk.q),
987 .ds (),
988
989 // to register interface (read)
990 .qs (ctrl_slpbk_qs)
991 );
992
993 // F[llpbk]: 5:5
994 prim_subreg #(
995 .DW (1),
996 .SwAccess(prim_subreg_pkg::SwAccessRW),
997 .RESVAL (1'h0),
998 .Mubi (1'b0)
999 ) u_ctrl_llpbk (
1000 .clk_i (clk_i),
1001 .rst_ni (rst_ni),
1002
1003 // from register interface
1004 .we (ctrl_we),
1005 .wd (ctrl_llpbk_wd),
1006
1007 // from internal hardware
1008 .de (1'b0),
1009 .d ('0),
1010
1011 // to internal hardware
1012 .qe (),
1013 .q (reg2hw.ctrl.llpbk.q),
1014 .ds (),
1015
1016 // to register interface (read)
1017 .qs (ctrl_llpbk_qs)
1018 );
1019
1020 // F[parity_en]: 6:6
1021 prim_subreg #(
1022 .DW (1),
1023 .SwAccess(prim_subreg_pkg::SwAccessRW),
1024 .RESVAL (1'h0),
1025 .Mubi (1'b0)
1026 ) u_ctrl_parity_en (
1027 .clk_i (clk_i),
1028 .rst_ni (rst_ni),
1029
1030 // from register interface
1031 .we (ctrl_we),
1032 .wd (ctrl_parity_en_wd),
1033
1034 // from internal hardware
1035 .de (1'b0),
1036 .d ('0),
1037
1038 // to internal hardware
1039 .qe (),
1040 .q (reg2hw.ctrl.parity_en.q),
1041 .ds (),
1042
1043 // to register interface (read)
1044 .qs (ctrl_parity_en_qs)
1045 );
1046
1047 // F[parity_odd]: 7:7
1048 prim_subreg #(
1049 .DW (1),
1050 .SwAccess(prim_subreg_pkg::SwAccessRW),
1051 .RESVAL (1'h0),
1052 .Mubi (1'b0)
1053 ) u_ctrl_parity_odd (
1054 .clk_i (clk_i),
1055 .rst_ni (rst_ni),
1056
1057 // from register interface
1058 .we (ctrl_we),
1059 .wd (ctrl_parity_odd_wd),
1060
1061 // from internal hardware
1062 .de (1'b0),
1063 .d ('0),
1064
1065 // to internal hardware
1066 .qe (),
1067 .q (reg2hw.ctrl.parity_odd.q),
1068 .ds (),
1069
1070 // to register interface (read)
1071 .qs (ctrl_parity_odd_qs)
1072 );
1073
1074 // F[rxblvl]: 9:8
1075 prim_subreg #(
1076 .DW (2),
1077 .SwAccess(prim_subreg_pkg::SwAccessRW),
1078 .RESVAL (2'h0),
1079 .Mubi (1'b0)
1080 ) u_ctrl_rxblvl (
1081 .clk_i (clk_i),
1082 .rst_ni (rst_ni),
1083
1084 // from register interface
1085 .we (ctrl_we),
1086 .wd (ctrl_rxblvl_wd),
1087
1088 // from internal hardware
1089 .de (1'b0),
1090 .d ('0),
1091
1092 // to internal hardware
1093 .qe (),
1094 .q (reg2hw.ctrl.rxblvl.q),
1095 .ds (),
1096
1097 // to register interface (read)
1098 .qs (ctrl_rxblvl_qs)
1099 );
1100
1101 // F[nco]: 31:16
1102 prim_subreg #(
1103 .DW (16),
1104 .SwAccess(prim_subreg_pkg::SwAccessRW),
1105 .RESVAL (16'h0),
1106 .Mubi (1'b0)
1107 ) u_ctrl_nco (
1108 .clk_i (clk_i),
1109 .rst_ni (rst_ni),
1110
1111 // from register interface
1112 .we (ctrl_we),
1113 .wd (ctrl_nco_wd),
1114
1115 // from internal hardware
1116 .de (1'b0),
1117 .d ('0),
1118
1119 // to internal hardware
1120 .qe (),
1121 .q (reg2hw.ctrl.nco.q),
1122 .ds (),
1123
1124 // to register interface (read)
1125 .qs (ctrl_nco_qs)
1126 );
1127
1128
1129 // R[status]: V(True)
1130 // F[txfull]: 0:0
1131 prim_subreg_ext #(
1132 .DW (1)
1133 ) u_status_txfull (
1134 .re (status_re),
1135 .we (1'b0),
1136 .wd ('0),
1137 .d (hw2reg.status.txfull.d),
1138 .qre (reg2hw.status.txfull.re),
1139 .qe (),
1140 .q (reg2hw.status.txfull.q),
1141 .ds (),
1142 .qs (status_txfull_qs)
1143 );
1144
1145 // F[rxfull]: 1:1
1146 prim_subreg_ext #(
1147 .DW (1)
1148 ) u_status_rxfull (
1149 .re (status_re),
1150 .we (1'b0),
1151 .wd ('0),
1152 .d (hw2reg.status.rxfull.d),
1153 .qre (reg2hw.status.rxfull.re),
1154 .qe (),
1155 .q (reg2hw.status.rxfull.q),
1156 .ds (),
1157 .qs (status_rxfull_qs)
1158 );
1159
1160 // F[txempty]: 2:2
1161 prim_subreg_ext #(
1162 .DW (1)
1163 ) u_status_txempty (
1164 .re (status_re),
1165 .we (1'b0),
1166 .wd ('0),
1167 .d (hw2reg.status.txempty.d),
1168 .qre (reg2hw.status.txempty.re),
1169 .qe (),
1170 .q (reg2hw.status.txempty.q),
1171 .ds (),
1172 .qs (status_txempty_qs)
1173 );
1174
1175 // F[txidle]: 3:3
1176 prim_subreg_ext #(
1177 .DW (1)
1178 ) u_status_txidle (
1179 .re (status_re),
1180 .we (1'b0),
1181 .wd ('0),
1182 .d (hw2reg.status.txidle.d),
1183 .qre (reg2hw.status.txidle.re),
1184 .qe (),
1185 .q (reg2hw.status.txidle.q),
1186 .ds (),
1187 .qs (status_txidle_qs)
1188 );
1189
1190 // F[rxidle]: 4:4
1191 prim_subreg_ext #(
1192 .DW (1)
1193 ) u_status_rxidle (
1194 .re (status_re),
1195 .we (1'b0),
1196 .wd ('0),
1197 .d (hw2reg.status.rxidle.d),
1198 .qre (reg2hw.status.rxidle.re),
1199 .qe (),
1200 .q (reg2hw.status.rxidle.q),
1201 .ds (),
1202 .qs (status_rxidle_qs)
1203 );
1204
1205 // F[rxempty]: 5:5
1206 prim_subreg_ext #(
1207 .DW (1)
1208 ) u_status_rxempty (
1209 .re (status_re),
1210 .we (1'b0),
1211 .wd ('0),
1212 .d (hw2reg.status.rxempty.d),
1213 .qre (reg2hw.status.rxempty.re),
1214 .qe (),
1215 .q (reg2hw.status.rxempty.q),
1216 .ds (),
1217 .qs (status_rxempty_qs)
1218 );
1219
1220
1221 // R[rdata]: V(True)
1222 prim_subreg_ext #(
1223 .DW (8)
1224 ) u_rdata (
1225 .re (rdata_re),
1226 .we (1'b0),
1227 .wd ('0),
1228 .d (hw2reg.rdata.d),
1229 .qre (reg2hw.rdata.re),
1230 .qe (),
1231 .q (reg2hw.rdata.q),
1232 .ds (),
1233 .qs (rdata_qs)
1234 );
1235
1236
1237 // R[wdata]: V(False)
1238 logic wdata_qe;
1239 logic [0:0] wdata_flds_we;
1240 prim_flop #(
1241 .Width(1),
1242 .ResetValue(0)
1243 ) u_wdata0_qe (
1244 .clk_i(clk_i),
1245 .rst_ni(rst_ni),
1246 .d_i(&wdata_flds_we),
1247 .q_o(wdata_qe)
1248 );
1249 prim_subreg #(
1250 .DW (8),
1251 .SwAccess(prim_subreg_pkg::SwAccessWO),
1252 .RESVAL (8'h0),
1253 .Mubi (1'b0)
1254 ) u_wdata (
1255 .clk_i (clk_i),
1256 .rst_ni (rst_ni),
1257
1258 // from register interface
1259 .we (wdata_we),
1260 .wd (wdata_wd),
1261
1262 // from internal hardware
1263 .de (1'b0),
1264 .d ('0),
1265
1266 // to internal hardware
1267 .qe (wdata_flds_we[0]),
1268 .q (reg2hw.wdata.q),
1269 .ds (),
1270
1271 // to register interface (read)
1272 .qs ()
1273 );
1274 1/1 assign reg2hw.wdata.qe = wdata_qe;
Tests: T1 T2 T3
1275
1276
1277 // R[fifo_ctrl]: V(False)
1278 logic fifo_ctrl_qe;
1279 logic [3:0] fifo_ctrl_flds_we;
1280 prim_flop #(
1281 .Width(1),
1282 .ResetValue(0)
1283 ) u_fifo_ctrl0_qe (
1284 .clk_i(clk_i),
1285 .rst_ni(rst_ni),
1286 .d_i(&fifo_ctrl_flds_we),
1287 .q_o(fifo_ctrl_qe)
1288 );
1289 // F[rxrst]: 0:0
1290 prim_subreg #(
1291 .DW (1),
1292 .SwAccess(prim_subreg_pkg::SwAccessWO),
1293 .RESVAL (1'h0),
1294 .Mubi (1'b0)
1295 ) u_fifo_ctrl_rxrst (
1296 .clk_i (clk_i),
1297 .rst_ni (rst_ni),
1298
1299 // from register interface
1300 .we (fifo_ctrl_we),
1301 .wd (fifo_ctrl_rxrst_wd),
1302
1303 // from internal hardware
1304 .de (1'b0),
1305 .d ('0),
1306
1307 // to internal hardware
1308 .qe (fifo_ctrl_flds_we[0]),
1309 .q (reg2hw.fifo_ctrl.rxrst.q),
1310 .ds (),
1311
1312 // to register interface (read)
1313 .qs ()
1314 );
1315 1/1 assign reg2hw.fifo_ctrl.rxrst.qe = fifo_ctrl_qe;
Tests: T1 T2 T3
1316
1317 // F[txrst]: 1:1
1318 prim_subreg #(
1319 .DW (1),
1320 .SwAccess(prim_subreg_pkg::SwAccessWO),
1321 .RESVAL (1'h0),
1322 .Mubi (1'b0)
1323 ) u_fifo_ctrl_txrst (
1324 .clk_i (clk_i),
1325 .rst_ni (rst_ni),
1326
1327 // from register interface
1328 .we (fifo_ctrl_we),
1329 .wd (fifo_ctrl_txrst_wd),
1330
1331 // from internal hardware
1332 .de (1'b0),
1333 .d ('0),
1334
1335 // to internal hardware
1336 .qe (fifo_ctrl_flds_we[1]),
1337 .q (reg2hw.fifo_ctrl.txrst.q),
1338 .ds (),
1339
1340 // to register interface (read)
1341 .qs ()
1342 );
1343 1/1 assign reg2hw.fifo_ctrl.txrst.qe = fifo_ctrl_qe;
Tests: T1 T2 T3
1344
1345 // F[rxilvl]: 4:2
1346 prim_subreg #(
1347 .DW (3),
1348 .SwAccess(prim_subreg_pkg::SwAccessRW),
1349 .RESVAL (3'h0),
1350 .Mubi (1'b0)
1351 ) u_fifo_ctrl_rxilvl (
1352 .clk_i (clk_i),
1353 .rst_ni (rst_ni),
1354
1355 // from register interface
1356 .we (fifo_ctrl_we),
1357 .wd (fifo_ctrl_rxilvl_wd),
1358
1359 // from internal hardware
1360 .de (hw2reg.fifo_ctrl.rxilvl.de),
1361 .d (hw2reg.fifo_ctrl.rxilvl.d),
1362
1363 // to internal hardware
1364 .qe (fifo_ctrl_flds_we[2]),
1365 .q (reg2hw.fifo_ctrl.rxilvl.q),
1366 .ds (),
1367
1368 // to register interface (read)
1369 .qs (fifo_ctrl_rxilvl_qs)
1370 );
1371 1/1 assign reg2hw.fifo_ctrl.rxilvl.qe = fifo_ctrl_qe;
Tests: T1 T2 T3
1372
1373 // F[txilvl]: 7:5
1374 prim_subreg #(
1375 .DW (3),
1376 .SwAccess(prim_subreg_pkg::SwAccessRW),
1377 .RESVAL (3'h0),
1378 .Mubi (1'b0)
1379 ) u_fifo_ctrl_txilvl (
1380 .clk_i (clk_i),
1381 .rst_ni (rst_ni),
1382
1383 // from register interface
1384 .we (fifo_ctrl_we),
1385 .wd (fifo_ctrl_txilvl_wd),
1386
1387 // from internal hardware
1388 .de (hw2reg.fifo_ctrl.txilvl.de),
1389 .d (hw2reg.fifo_ctrl.txilvl.d),
1390
1391 // to internal hardware
1392 .qe (fifo_ctrl_flds_we[3]),
1393 .q (reg2hw.fifo_ctrl.txilvl.q),
1394 .ds (),
1395
1396 // to register interface (read)
1397 .qs (fifo_ctrl_txilvl_qs)
1398 );
1399 1/1 assign reg2hw.fifo_ctrl.txilvl.qe = fifo_ctrl_qe;
Tests: T1 T2 T3
1400
1401
1402 // R[fifo_status]: V(True)
1403 // F[txlvl]: 7:0
1404 prim_subreg_ext #(
1405 .DW (8)
1406 ) u_fifo_status_txlvl (
1407 .re (fifo_status_re),
1408 .we (1'b0),
1409 .wd ('0),
1410 .d (hw2reg.fifo_status.txlvl.d),
1411 .qre (),
1412 .qe (),
1413 .q (),
1414 .ds (),
1415 .qs (fifo_status_txlvl_qs)
1416 );
1417
1418 // F[rxlvl]: 23:16
1419 prim_subreg_ext #(
1420 .DW (8)
1421 ) u_fifo_status_rxlvl (
1422 .re (fifo_status_re),
1423 .we (1'b0),
1424 .wd ('0),
1425 .d (hw2reg.fifo_status.rxlvl.d),
1426 .qre (),
1427 .qe (),
1428 .q (),
1429 .ds (),
1430 .qs (fifo_status_rxlvl_qs)
1431 );
1432
1433
1434 // R[ovrd]: V(False)
1435 // F[txen]: 0:0
1436 prim_subreg #(
1437 .DW (1),
1438 .SwAccess(prim_subreg_pkg::SwAccessRW),
1439 .RESVAL (1'h0),
1440 .Mubi (1'b0)
1441 ) u_ovrd_txen (
1442 .clk_i (clk_i),
1443 .rst_ni (rst_ni),
1444
1445 // from register interface
1446 .we (ovrd_we),
1447 .wd (ovrd_txen_wd),
1448
1449 // from internal hardware
1450 .de (1'b0),
1451 .d ('0),
1452
1453 // to internal hardware
1454 .qe (),
1455 .q (reg2hw.ovrd.txen.q),
1456 .ds (),
1457
1458 // to register interface (read)
1459 .qs (ovrd_txen_qs)
1460 );
1461
1462 // F[txval]: 1:1
1463 prim_subreg #(
1464 .DW (1),
1465 .SwAccess(prim_subreg_pkg::SwAccessRW),
1466 .RESVAL (1'h0),
1467 .Mubi (1'b0)
1468 ) u_ovrd_txval (
1469 .clk_i (clk_i),
1470 .rst_ni (rst_ni),
1471
1472 // from register interface
1473 .we (ovrd_we),
1474 .wd (ovrd_txval_wd),
1475
1476 // from internal hardware
1477 .de (1'b0),
1478 .d ('0),
1479
1480 // to internal hardware
1481 .qe (),
1482 .q (reg2hw.ovrd.txval.q),
1483 .ds (),
1484
1485 // to register interface (read)
1486 .qs (ovrd_txval_qs)
1487 );
1488
1489
1490 // R[val]: V(True)
1491 prim_subreg_ext #(
1492 .DW (16)
1493 ) u_val (
1494 .re (val_re),
1495 .we (1'b0),
1496 .wd ('0),
1497 .d (hw2reg.val.d),
1498 .qre (),
1499 .qe (),
1500 .q (),
1501 .ds (),
1502 .qs (val_qs)
1503 );
1504
1505
1506 // R[timeout_ctrl]: V(False)
1507 // F[val]: 23:0
1508 prim_subreg #(
1509 .DW (24),
1510 .SwAccess(prim_subreg_pkg::SwAccessRW),
1511 .RESVAL (24'h0),
1512 .Mubi (1'b0)
1513 ) u_timeout_ctrl_val (
1514 .clk_i (clk_i),
1515 .rst_ni (rst_ni),
1516
1517 // from register interface
1518 .we (timeout_ctrl_we),
1519 .wd (timeout_ctrl_val_wd),
1520
1521 // from internal hardware
1522 .de (1'b0),
1523 .d ('0),
1524
1525 // to internal hardware
1526 .qe (),
1527 .q (reg2hw.timeout_ctrl.val.q),
1528 .ds (),
1529
1530 // to register interface (read)
1531 .qs (timeout_ctrl_val_qs)
1532 );
1533
1534 // F[en]: 31:31
1535 prim_subreg #(
1536 .DW (1),
1537 .SwAccess(prim_subreg_pkg::SwAccessRW),
1538 .RESVAL (1'h0),
1539 .Mubi (1'b0)
1540 ) u_timeout_ctrl_en (
1541 .clk_i (clk_i),
1542 .rst_ni (rst_ni),
1543
1544 // from register interface
1545 .we (timeout_ctrl_we),
1546 .wd (timeout_ctrl_en_wd),
1547
1548 // from internal hardware
1549 .de (1'b0),
1550 .d ('0),
1551
1552 // to internal hardware
1553 .qe (),
1554 .q (reg2hw.timeout_ctrl.en.q),
1555 .ds (),
1556
1557 // to register interface (read)
1558 .qs (timeout_ctrl_en_qs)
1559 );
1560
1561
1562
1563 logic [12:0] addr_hit;
1564 always_comb begin
1565 1/1 addr_hit = '0;
Tests: T1 T2 T3
1566 1/1 addr_hit[ 0] = (reg_addr == UART_INTR_STATE_OFFSET);
Tests: T1 T2 T3
1567 1/1 addr_hit[ 1] = (reg_addr == UART_INTR_ENABLE_OFFSET);
Tests: T1 T2 T3
1568 1/1 addr_hit[ 2] = (reg_addr == UART_INTR_TEST_OFFSET);
Tests: T1 T2 T3
1569 1/1 addr_hit[ 3] = (reg_addr == UART_ALERT_TEST_OFFSET);
Tests: T1 T2 T3
1570 1/1 addr_hit[ 4] = (reg_addr == UART_CTRL_OFFSET);
Tests: T1 T2 T3
1571 1/1 addr_hit[ 5] = (reg_addr == UART_STATUS_OFFSET);
Tests: T1 T2 T3
1572 1/1 addr_hit[ 6] = (reg_addr == UART_RDATA_OFFSET);
Tests: T1 T2 T3
1573 1/1 addr_hit[ 7] = (reg_addr == UART_WDATA_OFFSET);
Tests: T1 T2 T3
1574 1/1 addr_hit[ 8] = (reg_addr == UART_FIFO_CTRL_OFFSET);
Tests: T1 T2 T3
1575 1/1 addr_hit[ 9] = (reg_addr == UART_FIFO_STATUS_OFFSET);
Tests: T1 T2 T3
1576 1/1 addr_hit[10] = (reg_addr == UART_OVRD_OFFSET);
Tests: T1 T2 T3
1577 1/1 addr_hit[11] = (reg_addr == UART_VAL_OFFSET);
Tests: T1 T2 T3
1578 1/1 addr_hit[12] = (reg_addr == UART_TIMEOUT_CTRL_OFFSET);
Tests: T1 T2 T3
1579 end
1580
1581 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T1 T2 T3
1582
1583 // Check sub-word write is permitted
1584 always_comb begin
1585 1/1 wr_err = (reg_we &
Tests: T1 T2 T3
1586 ((addr_hit[ 0] & (|(UART_PERMIT[ 0] & ~reg_be))) |
1587 (addr_hit[ 1] & (|(UART_PERMIT[ 1] & ~reg_be))) |
1588 (addr_hit[ 2] & (|(UART_PERMIT[ 2] & ~reg_be))) |
1589 (addr_hit[ 3] & (|(UART_PERMIT[ 3] & ~reg_be))) |
1590 (addr_hit[ 4] & (|(UART_PERMIT[ 4] & ~reg_be))) |
1591 (addr_hit[ 5] & (|(UART_PERMIT[ 5] & ~reg_be))) |
1592 (addr_hit[ 6] & (|(UART_PERMIT[ 6] & ~reg_be))) |
1593 (addr_hit[ 7] & (|(UART_PERMIT[ 7] & ~reg_be))) |
1594 (addr_hit[ 8] & (|(UART_PERMIT[ 8] & ~reg_be))) |
1595 (addr_hit[ 9] & (|(UART_PERMIT[ 9] & ~reg_be))) |
1596 (addr_hit[10] & (|(UART_PERMIT[10] & ~reg_be))) |
1597 (addr_hit[11] & (|(UART_PERMIT[11] & ~reg_be))) |
1598 (addr_hit[12] & (|(UART_PERMIT[12] & ~reg_be)))));
1599 end
1600
1601 // Generate write-enables
1602 1/1 assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
Tests: T1 T2 T3
1603
1604 1/1 assign intr_state_tx_done_wd = reg_wdata[2];
Tests: T1 T2 T3
1605
1606 1/1 assign intr_state_rx_overflow_wd = reg_wdata[3];
Tests: T1 T2 T3
1607
1608 1/1 assign intr_state_rx_frame_err_wd = reg_wdata[4];
Tests: T1 T2 T3
1609
1610 1/1 assign intr_state_rx_break_err_wd = reg_wdata[5];
Tests: T1 T2 T3
1611
1612 1/1 assign intr_state_rx_timeout_wd = reg_wdata[6];
Tests: T1 T2 T3
1613
1614 1/1 assign intr_state_rx_parity_err_wd = reg_wdata[7];
Tests: T1 T2 T3
1615 1/1 assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
Tests: T1 T2 T3
1616
1617 1/1 assign intr_enable_tx_watermark_wd = reg_wdata[0];
Tests: T1 T2 T3
1618
1619 1/1 assign intr_enable_rx_watermark_wd = reg_wdata[1];
Tests: T1 T2 T3
1620
1621 1/1 assign intr_enable_tx_done_wd = reg_wdata[2];
Tests: T1 T2 T3
1622
1623 1/1 assign intr_enable_rx_overflow_wd = reg_wdata[3];
Tests: T1 T2 T3
1624
1625 1/1 assign intr_enable_rx_frame_err_wd = reg_wdata[4];
Tests: T1 T2 T3
1626
1627 1/1 assign intr_enable_rx_break_err_wd = reg_wdata[5];
Tests: T1 T2 T3
1628
1629 1/1 assign intr_enable_rx_timeout_wd = reg_wdata[6];
Tests: T1 T2 T3
1630
1631 1/1 assign intr_enable_rx_parity_err_wd = reg_wdata[7];
Tests: T1 T2 T3
1632
1633 1/1 assign intr_enable_tx_empty_wd = reg_wdata[8];
Tests: T1 T2 T3
1634 1/1 assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
Tests: T1 T2 T3
1635
1636 1/1 assign intr_test_tx_watermark_wd = reg_wdata[0];
Tests: T1 T2 T3
1637
1638 1/1 assign intr_test_rx_watermark_wd = reg_wdata[1];
Tests: T1 T2 T3
1639
1640 1/1 assign intr_test_tx_done_wd = reg_wdata[2];
Tests: T1 T2 T3
1641
1642 1/1 assign intr_test_rx_overflow_wd = reg_wdata[3];
Tests: T1 T2 T3
1643
1644 1/1 assign intr_test_rx_frame_err_wd = reg_wdata[4];
Tests: T1 T2 T3
1645
1646 1/1 assign intr_test_rx_break_err_wd = reg_wdata[5];
Tests: T1 T2 T3
1647
1648 1/1 assign intr_test_rx_timeout_wd = reg_wdata[6];
Tests: T1 T2 T3
1649
1650 1/1 assign intr_test_rx_parity_err_wd = reg_wdata[7];
Tests: T1 T2 T3
1651
1652 1/1 assign intr_test_tx_empty_wd = reg_wdata[8];
Tests: T1 T2 T3
1653 1/1 assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
Tests: T1 T2 T3
1654
1655 1/1 assign alert_test_wd = reg_wdata[0];
Tests: T1 T2 T3
1656 1/1 assign ctrl_we = addr_hit[4] & reg_we & !reg_error;
Tests: T1 T2 T3
1657
1658 1/1 assign ctrl_tx_wd = reg_wdata[0];
Tests: T1 T2 T3
1659
1660 1/1 assign ctrl_rx_wd = reg_wdata[1];
Tests: T1 T2 T3
1661
1662 1/1 assign ctrl_nf_wd = reg_wdata[2];
Tests: T1 T2 T3
1663
1664 1/1 assign ctrl_slpbk_wd = reg_wdata[4];
Tests: T1 T2 T3
1665
1666 1/1 assign ctrl_llpbk_wd = reg_wdata[5];
Tests: T1 T2 T3
1667
1668 1/1 assign ctrl_parity_en_wd = reg_wdata[6];
Tests: T1 T2 T3
1669
1670 1/1 assign ctrl_parity_odd_wd = reg_wdata[7];
Tests: T1 T2 T3
1671
1672 1/1 assign ctrl_rxblvl_wd = reg_wdata[9:8];
Tests: T1 T2 T3
1673
1674 1/1 assign ctrl_nco_wd = reg_wdata[31:16];
Tests: T1 T2 T3
1675 1/1 assign status_re = addr_hit[5] & reg_re & !reg_error;
Tests: T1 T2 T3
1676 1/1 assign rdata_re = addr_hit[6] & reg_re & !reg_error;
Tests: T1 T2 T3
1677 1/1 assign wdata_we = addr_hit[7] & reg_we & !reg_error;
Tests: T1 T2 T3
1678
1679 1/1 assign wdata_wd = reg_wdata[7:0];
Tests: T1 T2 T3
1680 1/1 assign fifo_ctrl_we = addr_hit[8] & reg_we & !reg_error;
Tests: T1 T2 T3
1681
1682 1/1 assign fifo_ctrl_rxrst_wd = reg_wdata[0];
Tests: T1 T2 T3
1683
1684 1/1 assign fifo_ctrl_txrst_wd = reg_wdata[1];
Tests: T1 T2 T3
1685
1686 1/1 assign fifo_ctrl_rxilvl_wd = reg_wdata[4:2];
Tests: T1 T2 T3
1687
1688 1/1 assign fifo_ctrl_txilvl_wd = reg_wdata[7:5];
Tests: T1 T2 T3
1689 1/1 assign fifo_status_re = addr_hit[9] & reg_re & !reg_error;
Tests: T1 T2 T3
1690 1/1 assign ovrd_we = addr_hit[10] & reg_we & !reg_error;
Tests: T1 T2 T3
1691
1692 1/1 assign ovrd_txen_wd = reg_wdata[0];
Tests: T1 T2 T3
1693
1694 1/1 assign ovrd_txval_wd = reg_wdata[1];
Tests: T1 T2 T3
1695 1/1 assign val_re = addr_hit[11] & reg_re & !reg_error;
Tests: T1 T2 T3
1696 1/1 assign timeout_ctrl_we = addr_hit[12] & reg_we & !reg_error;
Tests: T1 T2 T3
1697
1698 1/1 assign timeout_ctrl_val_wd = reg_wdata[23:0];
Tests: T1 T2 T3
1699
1700 1/1 assign timeout_ctrl_en_wd = reg_wdata[31];
Tests: T1 T2 T3
1701
1702 // Assign write-enables to checker logic vector.
1703 always_comb begin
1704 1/1 reg_we_check = '0;
Tests: T1 T2 T3
1705 1/1 reg_we_check[0] = intr_state_we;
Tests: T1 T2 T3
1706 1/1 reg_we_check[1] = intr_enable_we;
Tests: T1 T2 T3
1707 1/1 reg_we_check[2] = intr_test_we;
Tests: T1 T2 T3
1708 1/1 reg_we_check[3] = alert_test_we;
Tests: T1 T2 T3
1709 1/1 reg_we_check[4] = ctrl_we;
Tests: T1 T2 T3
1710 1/1 reg_we_check[5] = 1'b0;
Tests: T1 T2 T3
1711 1/1 reg_we_check[6] = 1'b0;
Tests: T1 T2 T3
1712 1/1 reg_we_check[7] = wdata_we;
Tests: T1 T2 T3
1713 1/1 reg_we_check[8] = fifo_ctrl_we;
Tests: T1 T2 T3
1714 1/1 reg_we_check[9] = 1'b0;
Tests: T1 T2 T3
1715 1/1 reg_we_check[10] = ovrd_we;
Tests: T1 T2 T3
1716 1/1 reg_we_check[11] = 1'b0;
Tests: T1 T2 T3
1717 1/1 reg_we_check[12] = timeout_ctrl_we;
Tests: T1 T2 T3
1718 end
1719
1720 // Read data return
1721 always_comb begin
1722 1/1 reg_rdata_next = '0;
Tests: T1 T2 T3
1723 1/1 unique case (1'b1)
Tests: T1 T2 T3
1724 addr_hit[0]: begin
1725 1/1 reg_rdata_next[0] = intr_state_tx_watermark_qs;
Tests: T1 T2 T3
1726 1/1 reg_rdata_next[1] = intr_state_rx_watermark_qs;
Tests: T1 T2 T3
1727 1/1 reg_rdata_next[2] = intr_state_tx_done_qs;
Tests: T1 T2 T3
1728 1/1 reg_rdata_next[3] = intr_state_rx_overflow_qs;
Tests: T1 T2 T3
1729 1/1 reg_rdata_next[4] = intr_state_rx_frame_err_qs;
Tests: T1 T2 T3
1730 1/1 reg_rdata_next[5] = intr_state_rx_break_err_qs;
Tests: T1 T2 T3
1731 1/1 reg_rdata_next[6] = intr_state_rx_timeout_qs;
Tests: T1 T2 T3
1732 1/1 reg_rdata_next[7] = intr_state_rx_parity_err_qs;
Tests: T1 T2 T3
1733 1/1 reg_rdata_next[8] = intr_state_tx_empty_qs;
Tests: T1 T2 T3
1734 end
1735
1736 addr_hit[1]: begin
1737 1/1 reg_rdata_next[0] = intr_enable_tx_watermark_qs;
Tests: T1 T2 T3
1738 1/1 reg_rdata_next[1] = intr_enable_rx_watermark_qs;
Tests: T1 T2 T3
1739 1/1 reg_rdata_next[2] = intr_enable_tx_done_qs;
Tests: T1 T2 T3
1740 1/1 reg_rdata_next[3] = intr_enable_rx_overflow_qs;
Tests: T1 T2 T3
1741 1/1 reg_rdata_next[4] = intr_enable_rx_frame_err_qs;
Tests: T1 T2 T3
1742 1/1 reg_rdata_next[5] = intr_enable_rx_break_err_qs;
Tests: T1 T2 T3
1743 1/1 reg_rdata_next[6] = intr_enable_rx_timeout_qs;
Tests: T1 T2 T3
1744 1/1 reg_rdata_next[7] = intr_enable_rx_parity_err_qs;
Tests: T1 T2 T3
1745 1/1 reg_rdata_next[8] = intr_enable_tx_empty_qs;
Tests: T1 T2 T3
1746 end
1747
1748 addr_hit[2]: begin
1749 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
1750 1/1 reg_rdata_next[1] = '0;
Tests: T1 T2 T3
1751 1/1 reg_rdata_next[2] = '0;
Tests: T1 T2 T3
1752 1/1 reg_rdata_next[3] = '0;
Tests: T1 T2 T3
1753 1/1 reg_rdata_next[4] = '0;
Tests: T1 T2 T3
1754 1/1 reg_rdata_next[5] = '0;
Tests: T1 T2 T3
1755 1/1 reg_rdata_next[6] = '0;
Tests: T1 T2 T3
1756 1/1 reg_rdata_next[7] = '0;
Tests: T1 T2 T3
1757 1/1 reg_rdata_next[8] = '0;
Tests: T1 T2 T3
1758 end
1759
1760 addr_hit[3]: begin
1761 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
1762 end
1763
1764 addr_hit[4]: begin
1765 1/1 reg_rdata_next[0] = ctrl_tx_qs;
Tests: T1 T2 T3
1766 1/1 reg_rdata_next[1] = ctrl_rx_qs;
Tests: T1 T2 T3
1767 1/1 reg_rdata_next[2] = ctrl_nf_qs;
Tests: T1 T2 T3
1768 1/1 reg_rdata_next[4] = ctrl_slpbk_qs;
Tests: T1 T2 T3
1769 1/1 reg_rdata_next[5] = ctrl_llpbk_qs;
Tests: T1 T2 T3
1770 1/1 reg_rdata_next[6] = ctrl_parity_en_qs;
Tests: T1 T2 T3
1771 1/1 reg_rdata_next[7] = ctrl_parity_odd_qs;
Tests: T1 T2 T3
1772 1/1 reg_rdata_next[9:8] = ctrl_rxblvl_qs;
Tests: T1 T2 T3
1773 1/1 reg_rdata_next[31:16] = ctrl_nco_qs;
Tests: T1 T2 T3
1774 end
1775
1776 addr_hit[5]: begin
1777 1/1 reg_rdata_next[0] = status_txfull_qs;
Tests: T1 T2 T3
1778 1/1 reg_rdata_next[1] = status_rxfull_qs;
Tests: T1 T2 T3
1779 1/1 reg_rdata_next[2] = status_txempty_qs;
Tests: T1 T2 T3
1780 1/1 reg_rdata_next[3] = status_txidle_qs;
Tests: T1 T2 T3
1781 1/1 reg_rdata_next[4] = status_rxidle_qs;
Tests: T1 T2 T3
1782 1/1 reg_rdata_next[5] = status_rxempty_qs;
Tests: T1 T2 T3
1783 end
1784
1785 addr_hit[6]: begin
1786 1/1 reg_rdata_next[7:0] = rdata_qs;
Tests: T1 T2 T3
1787 end
1788
1789 addr_hit[7]: begin
1790 1/1 reg_rdata_next[7:0] = '0;
Tests: T1 T2 T3
1791 end
1792
1793 addr_hit[8]: begin
1794 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T3
1795 1/1 reg_rdata_next[1] = '0;
Tests: T1 T2 T3
1796 1/1 reg_rdata_next[4:2] = fifo_ctrl_rxilvl_qs;
Tests: T1 T2 T3
1797 1/1 reg_rdata_next[7:5] = fifo_ctrl_txilvl_qs;
Tests: T1 T2 T3
1798 end
1799
1800 addr_hit[9]: begin
1801 1/1 reg_rdata_next[7:0] = fifo_status_txlvl_qs;
Tests: T1 T2 T3
1802 1/1 reg_rdata_next[23:16] = fifo_status_rxlvl_qs;
Tests: T1 T2 T3
1803 end
1804
1805 addr_hit[10]: begin
1806 1/1 reg_rdata_next[0] = ovrd_txen_qs;
Tests: T1 T2 T3
1807 1/1 reg_rdata_next[1] = ovrd_txval_qs;
Tests: T1 T2 T3
1808 end
1809
1810 addr_hit[11]: begin
1811 1/1 reg_rdata_next[15:0] = val_qs;
Tests: T1 T2 T3
1812 end
1813
1814 addr_hit[12]: begin
1815 1/1 reg_rdata_next[23:0] = timeout_ctrl_val_qs;
Tests: T1 T2 T3
1816 1/1 reg_rdata_next[31] = timeout_ctrl_en_qs;
Tests: T1 T2 T3
1817 end
1818
1819 default: begin
1820 reg_rdata_next = '1;
1821 end
1822 endcase
1823 end
1824
1825 // shadow busy
1826 logic shadow_busy;
1827 assign shadow_busy = 1'b0;
1828
1829 // register busy
1830 unreachable assign reg_busy = shadow_busy;
1831
1832 // Unused signal tieoff
1833
1834 // wdata / byte enable are not always fully used
1835 // add a blanket unused statement to handle lint waivers
1836 logic unused_wdata;
1837 logic unused_be;
1838 1/1 assign unused_wdata = ^reg_wdata;
Tests: T1 T2 T3
1839 1/1 assign unused_be = ^reg_be;
Tests: T1 T2 T3
Cond Coverage for Module :
uart_reg_top
| Total | Covered | Percent |
|---|
| Conditions | 153 | 153 | 100.00 |
| Logical | 153 | 153 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (reg_we && ((!addrmiss)))
---1-- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T10,T31,T32 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 70
EXPRESSION (intg_err || reg_we_err)
----1--- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T8,T36,T39 |
| 1 | 0 | Covered | T77,T78,T79 |
LINE 77
EXPRESSION (err_q | intg_err | reg_we_err)
--1-- ----2--- -----3----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T8,T36,T39 |
| 0 | 1 | 0 | Covered | T77,T78,T79 |
| 1 | 0 | 0 | Covered | T8,T36,T39 |
LINE 119
EXPRESSION (addrmiss | wr_err | intg_err)
----1--- ---2-- ----3---
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 1 | Covered | T77,T78,T79 |
| 0 | 1 | 0 | Covered | T10,T31,T32 |
| 1 | 0 | 0 | Covered | T10,T31,T32 |
LINE 1566
EXPRESSION (reg_addr == uart_reg_pkg::UART_INTR_STATE_OFFSET)
-------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1567
EXPRESSION (reg_addr == uart_reg_pkg::UART_INTR_ENABLE_OFFSET)
-------------------------1-------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 1568
EXPRESSION (reg_addr == uart_reg_pkg::UART_INTR_TEST_OFFSET)
------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T8,T9 |
LINE 1569
EXPRESSION (reg_addr == uart_reg_pkg::UART_ALERT_TEST_OFFSET)
-------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T6,T9 |
LINE 1570
EXPRESSION (reg_addr == uart_reg_pkg::UART_CTRL_OFFSET)
----------------------1---------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1571
EXPRESSION (reg_addr == uart_reg_pkg::UART_STATUS_OFFSET)
-----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1572
EXPRESSION (reg_addr == uart_reg_pkg::UART_RDATA_OFFSET)
----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1573
EXPRESSION (reg_addr == uart_reg_pkg::UART_WDATA_OFFSET)
----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1574
EXPRESSION (reg_addr == uart_reg_pkg::UART_FIFO_CTRL_OFFSET)
------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 1575
EXPRESSION (reg_addr == uart_reg_pkg::UART_FIFO_STATUS_OFFSET)
-------------------------1-------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T6,T7 |
LINE 1576
EXPRESSION (reg_addr == uart_reg_pkg::UART_OVRD_OFFSET)
----------------------1---------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T5,T6 |
LINE 1577
EXPRESSION (reg_addr == uart_reg_pkg::UART_VAL_OFFSET)
---------------------1---------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T5,T6 |
LINE 1578
EXPRESSION (reg_addr == uart_reg_pkg::UART_TIMEOUT_CTRL_OFFSET)
--------------------------1-------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T5 |
LINE 1581
EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
---------1--------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 1581
SUB-EXPRESSION (reg_re || reg_we)
---1-- ---2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 1585
EXPRESSION
Number Term
1 reg_we &
2 ((addr_hit[0] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1 & (~reg_be))))) | (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))))
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T10,T31,T32 |
LINE 1585
SUB-EXPRESSION
Number Term
1 (addr_hit[0] & ((|(4'b0011 & (~reg_be))))) |
2 (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) |
3 (addr_hit[2] & ((|(4'b0011 & (~reg_be))))) |
4 (addr_hit[3] & ((|(4'b1 & (~reg_be))))) |
5 (addr_hit[4] & ((|(4'b1111 & (~reg_be))))) |
6 (addr_hit[5] & ((|(4'b1 & (~reg_be))))) |
7 (addr_hit[6] & ((|(4'b1 & (~reg_be))))) |
8 (addr_hit[7] & ((|(4'b1 & (~reg_be))))) |
9 (addr_hit[8] & ((|(4'b1 & (~reg_be))))) |
10 (addr_hit[9] & ((|(4'b0111 & (~reg_be))))) |
11 (addr_hit[10] & ((|(4'b1 & (~reg_be))))) |
12 (addr_hit[11] & ((|(4'b0011 & (~reg_be))))) |
13 (addr_hit[12] & ((|(4'b1111 & (~reg_be))))))
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | -9- | -10- | -11- | -12- | -13- | Status | Tests |
|---|
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | Covered | T5,T8,T9 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | Covered | T5,T6,T8 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | Covered | T5,T9,T10 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | Covered | T5,T6,T7 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | Covered | T5,T9,T10 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | Covered | T5,T6,T9 |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T3,T5 |
| 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T2,T5,T6 |
| 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T5,T9,T10 |
| 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T5,T9,T10 |
| 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T5,T8,T9 |
| 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T5,T8,T9 |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Covered | T1,T3,T4 |
LINE 1585
SUB-EXPRESSION (addr_hit[0] & ((|(4'b0011 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T3,T4 |
LINE 1585
SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T4,T5 |
| 1 | 1 | Covered | T5,T8,T9 |
LINE 1585
SUB-EXPRESSION (addr_hit[2] & ((|(4'b0011 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T5,T8,T9 |
| 1 | 1 | Covered | T5,T8,T9 |
LINE 1585
SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T5,T6,T9 |
| 1 | 1 | Covered | T5,T9,T10 |
LINE 1585
SUB-EXPRESSION (addr_hit[4] & ((|(4'b1111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T5,T9,T10 |
LINE 1585
SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T3,T4 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T2,T5,T6 |
LINE 1585
SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T3,T5 |
LINE 1585
SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T5,T6,T9 |
LINE 1585
SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
-----1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T4,T5 |
| 1 | 1 | Covered | T5,T9,T10 |
LINE 1585
SUB-EXPRESSION (addr_hit[9] & ((|(4'b0111 & (~reg_be)))))
-----1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T5,T7,T9 |
| 1 | 1 | Covered | T5,T6,T7 |
LINE 1585
SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
------1----- -----------2-----------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T5,T6 |
| 1 | 1 | Covered | T5,T9,T10 |
LINE 1585
SUB-EXPRESSION (addr_hit[11] & ((|(4'b0011 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T4,T5,T9 |
| 1 | 1 | Covered | T5,T6,T8 |
LINE 1585
SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
------1----- -------------2------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T4,T5 |
| 1 | 1 | Covered | T5,T8,T9 |
LINE 1602
EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T10,T31,T32 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1615
EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T4,T5 |
| 1 | 1 | 0 | Covered | T10,T31,T32 |
| 1 | 1 | 1 | Covered | T2,T4,T5 |
LINE 1634
EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T5,T8,T9 |
| 1 | 1 | 0 | Covered | T10,T31,T32 |
| 1 | 1 | 1 | Covered | T10,T43,T72 |
LINE 1653
EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T5,T6,T9 |
| 1 | 1 | 0 | Covered | T10,T31,T32 |
| 1 | 1 | 1 | Covered | T6,T37,T38 |
LINE 1656
EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T10,T31,T32 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1675
EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T80,T81,T82 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1676
EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T77,T83,T84 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1677
EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T10,T31,T32 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 1680
EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T4,T5 |
| 1 | 1 | 0 | Covered | T10,T31,T32 |
| 1 | 1 | 1 | Covered | T2,T4,T5 |
LINE 1689
EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
-----1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T5,T6,T7 |
| 1 | 1 | 0 | Covered | T79,T81 |
| 1 | 1 | 1 | Covered | T5,T7,T10 |
LINE 1690
EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T3,T5,T6 |
| 1 | 1 | 0 | Covered | T10,T31,T32 |
| 1 | 1 | 1 | Covered | T3,T22,T23 |
LINE 1695
EXPRESSION (addr_hit[11] & reg_re & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T4,T5,T6 |
| 1 | 1 | 0 | Covered | T77,T79,T80 |
| 1 | 1 | 1 | Covered | T4,T10,T21 |
LINE 1696
EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
------1----- ---2-- -------3------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T4,T5 |
| 1 | 1 | 0 | Covered | T10,T31,T32 |
| 1 | 1 | 1 | Covered | T2,T4,T5 |
Branch Coverage for Module :
uart_reg_top
| Line No. | Total | Covered | Percent |
| Branches |
|
19 |
19 |
100.00 |
| TERNARY |
1581 |
2 |
2 |
100.00 |
| IF |
68 |
3 |
3 |
100.00 |
| CASE |
1723 |
14 |
14 |
100.00 |
1581 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
68 if (!rst_ni) begin
-1-
69 err_q <= '0;
==>
70 end else if (intg_err || reg_we_err) begin
-2-
71 err_q <= 1'b1;
==>
72 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T8,T36,T39 |
| 0 |
0 |
Covered |
T1,T2,T3 |
1723 unique case (1'b1)
-1-
1724 addr_hit[0]: begin
1725 reg_rdata_next[0] = intr_state_tx_watermark_qs;
==>
1726 reg_rdata_next[1] = intr_state_rx_watermark_qs;
1727 reg_rdata_next[2] = intr_state_tx_done_qs;
1728 reg_rdata_next[3] = intr_state_rx_overflow_qs;
1729 reg_rdata_next[4] = intr_state_rx_frame_err_qs;
1730 reg_rdata_next[5] = intr_state_rx_break_err_qs;
1731 reg_rdata_next[6] = intr_state_rx_timeout_qs;
1732 reg_rdata_next[7] = intr_state_rx_parity_err_qs;
1733 reg_rdata_next[8] = intr_state_tx_empty_qs;
1734 end
1735
1736 addr_hit[1]: begin
1737 reg_rdata_next[0] = intr_enable_tx_watermark_qs;
==>
1738 reg_rdata_next[1] = intr_enable_rx_watermark_qs;
1739 reg_rdata_next[2] = intr_enable_tx_done_qs;
1740 reg_rdata_next[3] = intr_enable_rx_overflow_qs;
1741 reg_rdata_next[4] = intr_enable_rx_frame_err_qs;
1742 reg_rdata_next[5] = intr_enable_rx_break_err_qs;
1743 reg_rdata_next[6] = intr_enable_rx_timeout_qs;
1744 reg_rdata_next[7] = intr_enable_rx_parity_err_qs;
1745 reg_rdata_next[8] = intr_enable_tx_empty_qs;
1746 end
1747
1748 addr_hit[2]: begin
1749 reg_rdata_next[0] = '0;
==>
1750 reg_rdata_next[1] = '0;
1751 reg_rdata_next[2] = '0;
1752 reg_rdata_next[3] = '0;
1753 reg_rdata_next[4] = '0;
1754 reg_rdata_next[5] = '0;
1755 reg_rdata_next[6] = '0;
1756 reg_rdata_next[7] = '0;
1757 reg_rdata_next[8] = '0;
1758 end
1759
1760 addr_hit[3]: begin
1761 reg_rdata_next[0] = '0;
==>
1762 end
1763
1764 addr_hit[4]: begin
1765 reg_rdata_next[0] = ctrl_tx_qs;
==>
1766 reg_rdata_next[1] = ctrl_rx_qs;
1767 reg_rdata_next[2] = ctrl_nf_qs;
1768 reg_rdata_next[4] = ctrl_slpbk_qs;
1769 reg_rdata_next[5] = ctrl_llpbk_qs;
1770 reg_rdata_next[6] = ctrl_parity_en_qs;
1771 reg_rdata_next[7] = ctrl_parity_odd_qs;
1772 reg_rdata_next[9:8] = ctrl_rxblvl_qs;
1773 reg_rdata_next[31:16] = ctrl_nco_qs;
1774 end
1775
1776 addr_hit[5]: begin
1777 reg_rdata_next[0] = status_txfull_qs;
==>
1778 reg_rdata_next[1] = status_rxfull_qs;
1779 reg_rdata_next[2] = status_txempty_qs;
1780 reg_rdata_next[3] = status_txidle_qs;
1781 reg_rdata_next[4] = status_rxidle_qs;
1782 reg_rdata_next[5] = status_rxempty_qs;
1783 end
1784
1785 addr_hit[6]: begin
1786 reg_rdata_next[7:0] = rdata_qs;
==>
1787 end
1788
1789 addr_hit[7]: begin
1790 reg_rdata_next[7:0] = '0;
==>
1791 end
1792
1793 addr_hit[8]: begin
1794 reg_rdata_next[0] = '0;
==>
1795 reg_rdata_next[1] = '0;
1796 reg_rdata_next[4:2] = fifo_ctrl_rxilvl_qs;
1797 reg_rdata_next[7:5] = fifo_ctrl_txilvl_qs;
1798 end
1799
1800 addr_hit[9]: begin
1801 reg_rdata_next[7:0] = fifo_status_txlvl_qs;
==>
1802 reg_rdata_next[23:16] = fifo_status_rxlvl_qs;
1803 end
1804
1805 addr_hit[10]: begin
1806 reg_rdata_next[0] = ovrd_txen_qs;
==>
1807 reg_rdata_next[1] = ovrd_txval_qs;
1808 end
1809
1810 addr_hit[11]: begin
1811 reg_rdata_next[15:0] = val_qs;
==>
1812 end
1813
1814 addr_hit[12]: begin
1815 reg_rdata_next[23:0] = timeout_ctrl_val_qs;
==>
1816 reg_rdata_next[31] = timeout_ctrl_en_qs;
1817 end
1818
1819 default: begin
1820 reg_rdata_next = '1;
==>
Branches:
| -1- | Status | Tests |
| addr_hit[0] |
Covered |
T1,T2,T3 |
| addr_hit[1] |
Covered |
T1,T2,T3 |
| addr_hit[2] |
Covered |
T1,T2,T3 |
| addr_hit[3] |
Covered |
T1,T2,T3 |
| addr_hit[4] |
Covered |
T1,T2,T3 |
| addr_hit[5] |
Covered |
T1,T2,T3 |
| addr_hit[6] |
Covered |
T1,T2,T3 |
| addr_hit[7] |
Covered |
T1,T2,T3 |
| addr_hit[8] |
Covered |
T1,T2,T3 |
| addr_hit[9] |
Covered |
T1,T2,T3 |
| addr_hit[10] |
Covered |
T1,T2,T3 |
| addr_hit[11] |
Covered |
T1,T2,T3 |
| addr_hit[12] |
Covered |
T1,T2,T3 |
| default |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
uart_reg_top
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
en2addrHit |
2147483647 |
73109176 |
0 |
0 |
|
reAfterRv |
2147483647 |
73109176 |
0 |
0 |
|
rePulse |
2147483647 |
72513673 |
0 |
0 |
|
wePulse |
2147483647 |
595503 |
0 |
0 |
en2addrHit
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
73109176 |
0 |
0 |
| T1 |
22965 |
619 |
0 |
0 |
| T2 |
15041 |
116 |
0 |
0 |
| T3 |
33463 |
625 |
0 |
0 |
| T4 |
70188 |
4820 |
0 |
0 |
| T5 |
486351 |
301 |
0 |
0 |
| T6 |
1422 |
10 |
0 |
0 |
| T7 |
282770 |
624 |
0 |
0 |
| T8 |
3058 |
1 |
0 |
0 |
| T9 |
14527 |
1027 |
0 |
0 |
| T10 |
36902 |
199 |
0 |
0 |
reAfterRv
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
73109176 |
0 |
0 |
| T1 |
22965 |
619 |
0 |
0 |
| T2 |
15041 |
116 |
0 |
0 |
| T3 |
33463 |
625 |
0 |
0 |
| T4 |
70188 |
4820 |
0 |
0 |
| T5 |
486351 |
301 |
0 |
0 |
| T6 |
1422 |
10 |
0 |
0 |
| T7 |
282770 |
624 |
0 |
0 |
| T8 |
3058 |
1 |
0 |
0 |
| T9 |
14527 |
1027 |
0 |
0 |
| T10 |
36902 |
199 |
0 |
0 |
rePulse
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
72513673 |
0 |
0 |
| T1 |
22965 |
606 |
0 |
0 |
| T2 |
15041 |
101 |
0 |
0 |
| T3 |
33463 |
569 |
0 |
0 |
| T4 |
70188 |
4806 |
0 |
0 |
| T5 |
486351 |
127 |
0 |
0 |
| T6 |
1422 |
1 |
0 |
0 |
| T7 |
282770 |
544 |
0 |
0 |
| T8 |
3058 |
1 |
0 |
0 |
| T9 |
14527 |
1014 |
0 |
0 |
| T10 |
36902 |
88 |
0 |
0 |
wePulse
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
595503 |
0 |
0 |
| T1 |
22965 |
13 |
0 |
0 |
| T2 |
15041 |
15 |
0 |
0 |
| T3 |
33463 |
56 |
0 |
0 |
| T4 |
70188 |
14 |
0 |
0 |
| T5 |
486351 |
174 |
0 |
0 |
| T6 |
1422 |
9 |
0 |
0 |
| T7 |
282770 |
80 |
0 |
0 |
| T8 |
3058 |
0 |
0 |
0 |
| T9 |
14527 |
13 |
0 |
0 |
| T10 |
36902 |
111 |
0 |
0 |
| T11 |
0 |
346 |
0 |
0 |