Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/uart-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	914207	0	0
ctrl_rd_A	2147483647	22753	0	0
intr_enable_rd_A	2147483647	21455	0	0
ovrd_rd_A	2147483647	21764	0	0
timeout_ctrl_rd_A	2147483647	21595	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	914207	0	0
T10	36902	1618	0	0
T11	697261	0	0	0
T12	889555	0	0	0
T13	138698	0	0	0
T21	293235	0	0	0
T22	51591	0	0	0
T25	14831	0	0	0
T27	435914	0	0	0
T31	0	3058	0	0
T32	0	6547	0	0
T34	30714	0	0	0
T37	1037	0	0	0
T40	0	6716	0	0
T41	0	6230	0	0
T42	0	4654	0	0
T43	0	8532	0	0
T44	0	15074	0	0
T45	0	10451	0	0
T46	0	8895	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22753	0	0
T17	185507	0	0	0
T23	30654	0	0	0
T26	79290	0	0	0
T31	93562	151	0	0
T33	150745	0	0	0
T38	894	0	0	0
T39	26394	0	0	0
T42	0	522	0	0
T43	0	964	0	0
T46	0	398	0	0
T87	0	469	0	0
T88	0	1403	0	0
T89	0	287	0	0
T90	0	821	0	0
T91	0	833	0	0
T92	0	705	0	0
T93	407195	0	0	0
T94	356811	0	0	0
T95	156124	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21455	0	0
T17	185507	0	0	0
T23	30654	0	0	0
T26	79290	0	0	0
T31	93562	85	0	0
T33	150745	0	0	0
T38	894	0	0	0
T39	26394	0	0	0
T42	0	430	0	0
T43	0	1006	0	0
T46	0	348	0	0
T73	0	14	0	0
T87	0	509	0	0
T88	0	1335	0	0
T89	0	265	0	0
T90	0	695	0	0
T93	407195	0	0	0
T94	356811	0	0	0
T95	156124	0	0	0
T96	0	21	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21764	0	0
T17	185507	0	0	0
T23	30654	0	0	0
T26	79290	0	0	0
T31	93562	94	0	0
T33	150745	0	0	0
T38	894	0	0	0
T39	26394	0	0	0
T42	0	611	0	0
T43	0	1014	0	0
T46	0	379	0	0
T87	0	478	0	0
T88	0	1393	0	0
T89	0	281	0	0
T90	0	737	0	0
T91	0	776	0	0
T92	0	603	0	0
T93	407195	0	0	0
T94	356811	0	0	0
T95	156124	0	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21595	0	0
T17	185507	0	0	0
T23	30654	0	0	0
T26	79290	0	0	0
T31	93562	106	0	0
T33	150745	0	0	0
T38	894	0	0	0
T39	26394	0	0	0
T42	0	580	0	0
T43	0	927	0	0
T46	0	357	0	0
T87	0	448	0	0
T88	0	1237	0	0
T89	0	269	0	0
T90	0	864	0	0
T91	0	843	0	0
T92	0	639	0	0
T93	407195	0	0	0
T94	356811	0	0	0
T95	156124	0	0	0