Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	68886301	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

12786315

1

T1

16

T2

1

T3

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	80466759	1			T1	6101		T2	1		T3	1389
values[0x0]	584702	1			T1	13		T3	5		T4	9
values[0x1]	621155	1			T1	9		T3	6		T4	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47299404	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

34373212

1

T1

3078

T2

1

T3

713

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	285078	1			T1	26		T3	7		T5	2
valid_sources[0x01]	292277	1			T1	34		T3	7		T5	2
valid_sources[0x02]	462799	1			T1	22		T3	8		T5	2
valid_sources[0x03]	285450	1			T1	27		T3	11		T6	15
valid_sources[0x04]	322301	1			T1	35		T3	15		T5	4
valid_sources[0x05]	360373	1			T1	34		T3	2		T5	1
valid_sources[0x06]	295661	1			T1	24		T3	4		T5	1
valid_sources[0x07]	307913	1			T1	27		T3	6		T5	1
valid_sources[0x08]	289633	1			T1	17		T3	3		T6	7
valid_sources[0x09]	280324	1			T1	10		T3	11		T5	1
valid_sources[0x0a]	314042	1			T1	27		T5	2		T6	5
valid_sources[0x0b]	295221	1			T1	25		T3	2		T6	3
valid_sources[0x0c]	294941	1			T1	34		T3	11		T5	1
valid_sources[0x0d]	481276	1			T1	21		T3	2		T5	1
valid_sources[0x0e]	278868	1			T1	20		T3	12		T6	5
valid_sources[0x0f]	335111	1			T1	35		T3	5		T5	2
valid_sources[0x10]	330557	1			T1	25		T3	6		T5	2
valid_sources[0x11]	346315	1			T1	29		T3	9		T5	1
valid_sources[0x12]	302967	1			T1	28		T3	4		T6	9
valid_sources[0x13]	305190	1			T1	30		T3	5		T6	9
valid_sources[0x14]	286078	1			T1	15		T3	7		T5	1
valid_sources[0x15]	287434	1			T1	18		T3	4		T5	2
valid_sources[0x16]	289378	1			T1	43		T3	10		T5	2
valid_sources[0x17]	277918	1			T1	30		T3	5		T5	1
valid_sources[0x18]	387694	1			T1	17		T3	3		T5	1
valid_sources[0x19]	347435	1			T1	20		T3	10		T5	2
valid_sources[0x1a]	279837	1			T1	19		T3	6		T6	9
valid_sources[0x1b]	336687	1			T1	22		T3	1		T5	2
valid_sources[0x1c]	314954	1			T1	16		T3	8		T5	1
valid_sources[0x1d]	298587	1			T1	26		T3	12		T5	1
valid_sources[0x1e]	290006	1			T1	20		T3	18		T5	3
valid_sources[0x1f]	277908	1			T1	42		T3	3		T5	1
valid_sources[0x20]	374283	1			T1	20		T3	2		T6	7
valid_sources[0x21]	316743	1			T1	30		T3	8		T6	5
valid_sources[0x22]	335693	1			T1	21		T3	2		T6	8
valid_sources[0x23]	285243	1			T1	32		T3	6		T6	4
valid_sources[0x24]	342776	1			T1	16		T3	4		T6	7
valid_sources[0x25]	284642	1			T1	14		T5	1		T6	5
valid_sources[0x26]	292136	1			T1	23		T3	3		T5	2
valid_sources[0x27]	313691	1			T1	29		T3	5		T6	5
valid_sources[0x28]	413639	1			T1	33		T3	14		T5	2
valid_sources[0x29]	296305	1			T1	22		T3	4		T5	2
valid_sources[0x2a]	470532	1			T1	28		T3	2		T6	9
valid_sources[0x2b]	394280	1			T1	21		T3	9		T5	1
valid_sources[0x2c]	276999	1			T1	28		T3	4		T5	1
valid_sources[0x2d]	311770	1			T1	29		T3	17		T6	6
valid_sources[0x2e]	371744	1			T1	20		T3	7		T5	1
valid_sources[0x2f]	290675	1			T1	18		T3	4		T5	3
valid_sources[0x30]	296488	1			T1	13		T3	3		T5	2
valid_sources[0x31]	318423	1			T1	24		T3	3		T5	1
valid_sources[0x32]	297292	1			T1	22		T3	1		T5	5
valid_sources[0x33]	314467	1			T1	20		T3	19		T5	1
valid_sources[0x34]	286551	1			T1	28		T3	12		T5	1
valid_sources[0x35]	301381	1			T1	27		T3	3		T6	5
valid_sources[0x36]	295717	1			T1	21		T3	4		T5	1
valid_sources[0x37]	298901	1			T1	23		T3	7		T6	4
valid_sources[0x38]	278541	1			T1	21		T3	4		T5	3
valid_sources[0x39]	393208	1			T1	21		T3	1		T5	4
valid_sources[0x3a]	327613	1			T1	22		T3	9		T5	3
valid_sources[0x3b]	424736	1			T1	34		T3	7		T6	6
valid_sources[0x3c]	294488	1			T1	25		T3	2		T5	3
valid_sources[0x3d]	335324	1			T1	40		T3	13		T6	16
valid_sources[0x3e]	340015	1			T1	31		T3	5		T5	2
valid_sources[0x3f]	372632	1			T1	28		T3	2		T6	20
valid_sources[0x40]	278855	1			T1	24		T3	15		T5	1
valid_sources[0x41]	277924	1			T1	22		T3	14		T6	13
valid_sources[0x42]	414557	1			T1	18		T3	8		T6	11
valid_sources[0x43]	298975	1			T1	26		T3	6		T5	2
valid_sources[0x44]	347623	1			T1	13		T3	6		T5	2
valid_sources[0x45]	317493	1			T1	16		T5	1		T6	4
valid_sources[0x46]	319857	1			T1	21		T3	2		T5	5
valid_sources[0x47]	276654	1			T1	22		T3	8		T5	1
valid_sources[0x48]	379240	1			T1	33		T3	3		T5	1
valid_sources[0x49]	281245	1			T1	23		T3	5		T6	10
valid_sources[0x4a]	323356	1			T1	23		T3	15		T5	1
valid_sources[0x4b]	356696	1			T1	21		T3	6		T5	1
valid_sources[0x4c]	449559	1			T1	18		T3	1		T5	5
valid_sources[0x4d]	352610	1			T1	25		T3	13		T5	1
valid_sources[0x4e]	291490	1			T1	28		T3	3		T4	1
valid_sources[0x4f]	294281	1			T1	27		T3	13		T5	3
valid_sources[0x50]	306745	1			T1	15		T3	14		T5	2
valid_sources[0x51]	311360	1			T1	31		T5	3		T6	9
valid_sources[0x52]	331870	1			T1	31		T3	3		T5	1
valid_sources[0x53]	309429	1			T1	34		T3	8		T5	1
valid_sources[0x54]	344155	1			T1	22		T3	9		T5	1
valid_sources[0x55]	352085	1			T1	21		T3	6		T6	19
valid_sources[0x56]	361566	1			T1	21		T3	11		T5	1
valid_sources[0x57]	388196	1			T1	12		T3	1		T5	2
valid_sources[0x58]	298675	1			T1	30		T3	8		T6	9
valid_sources[0x59]	294002	1			T1	25		T3	5		T5	2
valid_sources[0x5a]	286846	1			T1	21		T3	4		T5	2
valid_sources[0x5b]	350963	1			T1	32		T3	3		T5	4
valid_sources[0x5c]	332399	1			T1	29		T3	4		T5	1
valid_sources[0x5d]	346631	1			T1	30		T3	4		T6	11
valid_sources[0x5e]	352413	1			T1	26		T3	5		T5	1
valid_sources[0x5f]	277340	1			T1	24		T3	11		T5	3
valid_sources[0x60]	295573	1			T1	27		T3	2		T5	1
valid_sources[0x61]	289679	1			T1	10		T3	4		T5	2
valid_sources[0x62]	319582	1			T1	18		T3	18		T5	1
valid_sources[0x63]	286596	1			T1	34		T3	15		T5	1
valid_sources[0x64]	298282	1			T1	15		T6	8		T8	33
valid_sources[0x65]	288326	1			T1	18		T3	8		T5	2
valid_sources[0x66]	276984	1			T1	31		T3	2		T5	1
valid_sources[0x67]	313809	1			T1	27		T5	1		T6	7
valid_sources[0x68]	338876	1			T1	16		T3	4		T5	2
valid_sources[0x69]	282213	1			T1	23		T3	7		T4	1
valid_sources[0x6a]	346096	1			T1	20		T3	3		T6	8
valid_sources[0x6b]	304853	1			T1	26		T5	1		T6	8
valid_sources[0x6c]	288232	1			T1	14		T3	11		T5	1
valid_sources[0x6d]	296389	1			T1	28		T3	10		T5	1
valid_sources[0x6e]	404632	1			T1	27		T3	5		T6	11
valid_sources[0x6f]	323748	1			T1	30		T3	4		T5	1
valid_sources[0x70]	321534	1			T1	28		T3	3		T5	1
valid_sources[0x71]	289864	1			T1	29		T3	8		T6	4
valid_sources[0x72]	295826	1			T1	33		T3	5		T6	8
valid_sources[0x73]	273996	1			T1	28		T3	7		T5	1
valid_sources[0x74]	280133	1			T1	9		T3	5		T5	2
valid_sources[0x75]	312641	1			T1	24		T3	9		T5	1
valid_sources[0x76]	335530	1			T1	20		T2	1		T3	5
valid_sources[0x77]	298543	1			T1	18		T3	6		T5	2
valid_sources[0x78]	294862	1			T1	19		T3	3		T5	2
valid_sources[0x79]	389320	1			T1	25		T3	2		T5	1
valid_sources[0x7a]	353698	1			T1	32		T3	21		T6	10
valid_sources[0x7b]	339003	1			T1	22		T3	5		T5	1
valid_sources[0x7c]	293255	1			T1	25		T3	2		T6	8
valid_sources[0x7d]	292486	1			T1	16		T3	5		T5	3
valid_sources[0x7e]	302702	1			T1	23		T3	1		T6	12
valid_sources[0x7f]	271554	1			T1	15		T3	1		T6	8
valid_sources[0x80]	275814	1			T1	22		T3	5		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

12023336

1

T1

1

T2

1

T4

1

values[0x0]

all_enables

biggest_size

405367

1

T1

9

T3

3

T4

2

values[0x1]

all_enables

biggest_size

357612

1

T1

6

T3

4

T4

1