Unified Coverage Report :: Module :: uart_csr_assert_fpv

Module : uart_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/uart-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_uart_csr_assert_0/uart_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.uart_csr_assert	100.00						100.00

---

Module Instance : tb.dut.uart_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : uart_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	953226	0	0
ctrl_rd_A	2147483647	22059	0	0
intr_enable_rd_A	2147483647	21499	0	0
ovrd_rd_A	2147483647	21186	0	0
timeout_ctrl_rd_A	2147483647	21251	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	953226	0	0
T18	303412	7847	0	0
T25	96721	0	0	0
T26	164775	5837	0	0
T27	0	8597	0	0
T30	0	3899	0	0
T31	0	7543	0	0
T32	0	6698	0	0
T33	0	19373	0	0
T34	0	16672	0	0
T35	0	8364	0	0
T36	0	9970	0	0
T37	223638	0	0	0
T38	946	0	0	0
T39	131940	0	0	0
T40	12525	0	0	0
T41	132342	0	0	0
T42	235855	0	0	0
T43	168717	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22059	0	0
T18	303412	1183	0	0
T25	96721	0	0	0
T26	164775	0	0	0
T30	0	434	0	0
T31	0	943	0	0
T37	223638	0	0	0
T38	946	0	0	0
T39	131940	0	0	0
T40	12525	0	0	0
T41	132342	0	0	0
T42	235855	0	0	0
T43	168717	0	0	0
T87	0	1133	0	0
T88	0	515	0	0
T89	0	586	0	0
T90	0	445	0	0
T91	0	656	0	0
T92	0	157	0	0
T93	0	309	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21499	0	0
T18	303412	1055	0	0
T25	96721	0	0	0
T26	164775	0	0	0
T30	0	330	0	0
T31	0	906	0	0
T37	223638	0	0	0
T38	946	0	0	0
T39	131940	0	0	0
T40	12525	0	0	0
T41	132342	0	0	0
T42	235855	0	0	0
T43	168717	0	0	0
T87	0	955	0	0
T88	0	416	0	0
T89	0	470	0	0
T90	0	461	0	0
T91	0	581	0	0
T94	0	39	0	0
T95	0	19	0	0

ovrd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21186	0	0
T18	303412	1103	0	0
T25	96721	0	0	0
T26	164775	0	0	0
T30	0	424	0	0
T31	0	915	0	0
T37	223638	0	0	0
T38	946	0	0	0
T39	131940	0	0	0
T40	12525	0	0	0
T41	132342	0	0	0
T42	235855	0	0	0
T43	168717	0	0	0
T87	0	984	0	0
T88	0	525	0	0
T89	0	561	0	0
T90	0	469	0	0
T91	0	696	0	0
T92	0	151	0	0
T93	0	318	0	0

timeout_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21251	0	0
T18	303412	1070	0	0
T25	96721	0	0	0
T26	164775	0	0	0
T30	0	449	0	0
T31	0	936	0	0
T37	223638	0	0	0
T38	946	0	0	0
T39	131940	0	0	0
T40	12525	0	0	0
T41	132342	0	0	0
T42	235855	0	0	0
T43	168717	0	0	0
T87	0	1108	0	0
T88	0	509	0	0
T89	0	590	0	0
T90	0	553	0	0
T91	0	666	0	0
T92	0	141	0	0
T93	0	277	0	0