Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	83465	1			T1	2		T2	2		T3	1
all_values[1]	83465	1			T1	2		T2	2		T3	1
all_values[2]	83465	1			T1	2		T2	2		T3	1
all_values[3]	83465	1			T1	2		T2	2		T3	1
all_values[4]	83465	1			T1	2		T2	2		T3	1
all_values[5]	83465	1			T1	2		T2	2		T3	1
all_values[6]	83465	1			T1	2		T2	2		T3	1
all_values[7]	83465	1			T1	2		T2	2		T3	1
all_values[8]	83465	1			T1	2		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

377357

1

T1

18

T2

18

T3

5

auto[1]

373828

1

T3

4

T4

10

T8

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

676061

1

T1

13

T2

13

T3

7

auto[1]

75124

1

T1

5

T2

5

T3

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	21829	1			T75	1		T18	2		T130	4
all_values[0]	auto[0]	auto[1]	17173	1			T1	2		T2	2		T3	1
all_values[0]	auto[1]	auto[0]	24920	1			T4	1		T11	4		T18	1
all_values[0]	auto[1]	auto[1]	19543	1			T4	2		T8	1		T10	1
all_values[1]	auto[0]	auto[0]	43422	1			T1	2		T2	2		T4	3
all_values[1]	auto[0]	auto[1]	1390	1			T12	5		T18	6		T45	6
all_values[1]	auto[1]	auto[0]	37322	1			T3	1		T11	7		T12	19
all_values[1]	auto[1]	auto[1]	1331	1			T12	25		T18	4		T17	8
all_values[2]	auto[0]	auto[0]	42225	1			T1	1		T2	1		T4	2
all_values[2]	auto[0]	auto[1]	2357	1			T1	1		T2	1		T4	1
all_values[2]	auto[1]	auto[0]	36853	1			T3	1		T10	1		T11	6
all_values[2]	auto[1]	auto[1]	2030	1			T16	1		T75	1		T130	8
all_values[3]	auto[0]	auto[0]	42122	1			T1	2		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	223	1			T18	2		T17	1		T35	4
all_values[3]	auto[1]	auto[0]	40869	1			T8	1		T11	1		T12	42
all_values[3]	auto[1]	auto[1]	251	1			T11	1		T12	2		T18	2
all_values[4]	auto[0]	auto[0]	38770	1			T1	2		T2	2		T5	2
all_values[4]	auto[0]	auto[1]	340	1			T18	1		T17	1		T108	2
all_values[4]	auto[1]	auto[0]	44044	1			T3	1		T4	3		T8	1
all_values[4]	auto[1]	auto[1]	311	1			T12	16		T35	3		T36	3
all_values[5]	auto[0]	auto[0]	41114	1			T1	2		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	145	1			T35	7		T36	2		T38	3
all_values[5]	auto[1]	auto[0]	42077	1			T4	1		T11	3		T13	2
all_values[5]	auto[1]	auto[1]	129	1			T18	1		T35	2		T36	3
all_values[6]	auto[0]	auto[0]	41469	1			T1	2		T2	2		T3	1
all_values[6]	auto[0]	auto[1]	161	1			T18	1		T35	4		T36	3
all_values[6]	auto[1]	auto[0]	41707	1			T11	1		T12	59		T43	23
all_values[6]	auto[1]	auto[1]	128	1			T18	3		T35	3		T36	1
all_values[7]	auto[0]	auto[0]	42721	1			T1	2		T2	2		T3	1
all_values[7]	auto[0]	auto[1]	281	1			T18	2		T17	1		T25	1
all_values[7]	auto[1]	auto[0]	40162	1			T8	1		T10	1		T11	9
all_values[7]	auto[1]	auto[1]	301	1			T18	1		T25	1		T111	3
all_values[8]	auto[0]	auto[0]	26830	1			T11	6		T75	4		T18	2
all_values[8]	auto[0]	auto[1]	14785	1			T1	2		T2	2		T5	2
all_values[8]	auto[1]	auto[0]	27605	1			T4	1		T18	2		T131	3
all_values[8]	auto[1]	auto[1]	14245	1			T3	1		T4	2		T8	1