Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.10 99.08 97.65 100.00 98.35 100.00 99.53


Total tests in report: 1311
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
69.62 69.62 93.98 93.98 71.88 71.88 62.25 62.25 90.59 90.59 94.40 94.40 4.65 4.65 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_loopback.2366518009
79.79 10.16 97.96 3.98 90.47 18.59 88.38 26.14 93.65 3.06 95.87 1.47 12.40 7.74 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.2727720527
82.85 3.06 98.37 0.41 91.88 1.41 95.96 7.58 95.29 1.65 96.17 0.29 19.44 7.04 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.1735355411
85.04 2.19 98.37 0.00 91.88 0.00 95.96 0.00 95.29 0.00 96.17 0.00 32.58 13.14 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_stress_all.1647609186
86.43 1.38 98.37 0.00 91.88 0.00 95.96 0.00 95.29 0.00 96.17 0.00 40.89 8.31 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_stress_all.3237622991
87.68 1.25 98.67 0.31 94.71 2.82 97.22 1.26 96.47 1.18 96.17 0.00 42.83 1.94 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_intr.156351167
88.71 1.03 98.98 0.31 96.12 1.41 97.22 0.00 98.12 1.65 96.17 0.00 45.65 2.82 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_stress_all_with_rand_reset.2120839309
89.70 0.99 98.98 0.00 96.12 0.00 97.22 0.00 98.12 0.00 96.17 0.00 51.59 5.94 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_stress_all.4241745075
90.58 0.88 98.98 0.00 96.12 0.00 97.22 0.00 98.12 0.00 96.17 0.00 56.90 5.31 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_rx_parity_err.4294262015
91.35 0.77 98.98 0.00 96.12 0.00 97.22 0.00 98.12 0.00 96.17 0.00 61.50 4.61 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_fifo_full.1844079740
92.01 0.66 98.98 0.00 96.12 0.00 97.22 0.00 98.12 0.00 96.17 0.00 65.48 3.97 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_long_xfer_wo_dly.416870578
92.67 0.65 98.98 0.00 96.12 0.00 97.22 0.00 98.12 0.00 96.17 0.00 69.41 3.93 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_stress_all.543754756
93.27 0.60 99.08 0.10 96.47 0.35 99.75 2.53 98.35 0.24 96.46 0.29 69.52 0.11 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_sec_cm.2205244493
93.80 0.53 99.08 0.00 96.47 0.00 99.75 0.00 98.35 0.00 96.46 0.00 72.70 3.18 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_fifo_overflow.87616560
94.26 0.46 99.08 0.00 96.47 0.00 99.75 0.00 98.35 0.00 96.46 0.00 75.46 2.75 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_stress_all.1079000547
94.70 0.44 99.08 0.00 96.47 0.00 99.75 0.00 98.35 0.00 96.46 0.00 78.08 2.62 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_fifo_overflow.3205372370
95.06 0.36 99.08 0.00 96.47 0.00 99.75 0.00 98.35 0.00 96.46 0.00 80.22 2.14 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_stress_all.3917022316
95.39 0.34 99.08 0.00 96.47 0.00 99.75 0.00 98.35 0.00 96.46 0.00 82.25 2.03 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_fifo_reset.1871749652
95.70 0.30 99.08 0.00 96.47 0.00 99.75 0.00 98.35 0.00 96.46 0.00 84.06 1.81 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.3739045453
95.99 0.29 99.08 0.00 96.47 0.00 99.75 0.00 98.35 0.00 98.23 1.77 84.06 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_rw.1875897085
96.25 0.26 99.08 0.00 96.47 0.00 99.75 0.00 98.35 0.00 99.41 1.18 84.47 0.41 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.3248654564
96.51 0.26 99.08 0.00 96.47 0.00 99.75 0.00 98.35 0.00 99.71 0.29 85.73 1.26 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_perf.3989417392
96.72 0.21 99.08 0.00 96.47 0.00 99.75 0.00 98.35 0.00 99.71 0.00 86.97 1.24 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_stress_all_with_rand_reset.2045035085
96.92 0.20 99.08 0.00 96.47 0.00 99.75 0.00 98.35 0.00 99.71 0.00 88.19 1.22 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_tx_rx.504763709
97.09 0.17 99.08 0.00 96.47 0.00 99.75 0.00 98.35 0.00 99.71 0.00 89.18 0.99 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.3050706338
97.23 0.14 99.08 0.00 96.47 0.00 99.75 0.00 98.35 0.00 99.71 0.00 90.02 0.84 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_noise_filter.2747498954
97.35 0.12 99.08 0.00 97.06 0.59 99.75 0.00 98.35 0.00 99.71 0.00 90.18 0.16 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_intg_err.1389784498
97.47 0.12 99.08 0.00 97.06 0.00 99.75 0.00 98.35 0.00 99.71 0.00 90.90 0.72 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_rx_parity_err.1722506208
97.59 0.11 99.08 0.00 97.06 0.00 99.75 0.00 98.35 0.00 99.71 0.00 91.58 0.68 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_fifo_full.1610454746
97.69 0.11 99.08 0.00 97.06 0.00 99.75 0.00 98.35 0.00 99.71 0.00 92.21 0.63 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_perf.4155065716
97.79 0.10 99.08 0.00 97.41 0.35 100.00 0.25 98.35 0.00 99.71 0.00 92.21 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_alert_test.921200671
97.88 0.09 99.08 0.00 97.41 0.00 100.00 0.00 98.35 0.00 99.71 0.00 92.75 0.54 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_stress_all.3946869602
97.97 0.08 99.08 0.00 97.41 0.00 100.00 0.00 98.35 0.00 99.71 0.00 93.25 0.50 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_fifo_full.298415221
98.04 0.07 99.08 0.00 97.41 0.00 100.00 0.00 98.35 0.00 99.71 0.00 93.68 0.43 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_fifo_reset.3472090600
98.11 0.07 99.08 0.00 97.41 0.00 100.00 0.00 98.35 0.00 99.71 0.00 94.08 0.41 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.2456811775
98.17 0.06 99.08 0.00 97.41 0.00 100.00 0.00 98.35 0.00 99.71 0.00 94.45 0.36 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/28.uart_stress_all.158196447
98.22 0.06 99.08 0.00 97.41 0.00 100.00 0.00 98.35 0.00 99.71 0.00 94.78 0.34 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_noise_filter.3971102864
98.27 0.05 99.08 0.00 97.41 0.00 100.00 0.00 98.35 0.00 100.00 0.29 94.78 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_aliasing.4066565047
98.32 0.05 99.08 0.00 97.41 0.00 100.00 0.00 98.35 0.00 100.00 0.00 95.08 0.29 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_fifo_overflow.2514223448
98.37 0.05 99.08 0.00 97.41 0.00 100.00 0.00 98.35 0.00 100.00 0.00 95.35 0.27 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_stress_all.1903488071
98.41 0.04 99.08 0.00 97.41 0.00 100.00 0.00 98.35 0.00 100.00 0.00 95.60 0.25 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.1749330763
98.45 0.04 99.08 0.00 97.41 0.00 100.00 0.00 98.35 0.00 100.00 0.00 95.85 0.25 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_tx_rx.2095193182
98.49 0.04 99.08 0.00 97.41 0.00 100.00 0.00 98.35 0.00 100.00 0.00 96.07 0.23 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_perf.3868055779
98.52 0.03 99.08 0.00 97.41 0.00 100.00 0.00 98.35 0.00 100.00 0.00 96.27 0.20 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/42.uart_fifo_reset.1943236971
98.55 0.03 99.08 0.00 97.41 0.00 100.00 0.00 98.35 0.00 100.00 0.00 96.46 0.18 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_fifo_overflow.1006420333
98.58 0.03 99.08 0.00 97.53 0.12 100.00 0.00 98.35 0.00 100.00 0.00 96.50 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_intg_err.618673121
98.60 0.03 99.08 0.00 97.53 0.00 100.00 0.00 98.35 0.00 100.00 0.00 96.66 0.16 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_fifo_reset.2114195492
98.63 0.03 99.08 0.00 97.53 0.00 100.00 0.00 98.35 0.00 100.00 0.00 96.82 0.16 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_stress_all.702544190
98.66 0.03 99.08 0.00 97.53 0.00 100.00 0.00 98.35 0.00 100.00 0.00 96.97 0.16 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_stress_all.3082036126
98.68 0.03 99.08 0.00 97.53 0.00 100.00 0.00 98.35 0.00 100.00 0.00 97.13 0.16 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/260.uart_fifo_reset.1565143065
98.71 0.02 99.08 0.00 97.53 0.00 100.00 0.00 98.35 0.00 100.00 0.00 97.27 0.14 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/24.uart_fifo_reset.2744796828
98.73 0.02 99.08 0.00 97.53 0.00 100.00 0.00 98.35 0.00 100.00 0.00 97.40 0.14 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/298.uart_fifo_reset.1120178206
98.75 0.02 99.08 0.00 97.65 0.12 100.00 0.00 98.35 0.00 100.00 0.00 97.40 0.00 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_intg_err.1765275676
98.77 0.02 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 97.52 0.11 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_intr.2248522935
98.79 0.02 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 97.63 0.11 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_tx_rx.1630780459
98.80 0.02 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 97.72 0.09 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_fifo_full.4120855692
98.82 0.02 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 97.81 0.09 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_rx_parity_err.2000599031
98.83 0.02 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 97.90 0.09 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/125.uart_fifo_reset.276718307
98.85 0.02 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 97.99 0.09 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/53.uart_fifo_reset.2182471667
98.86 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.06 0.07 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/109.uart_fifo_reset.2878504210
98.87 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.13 0.07 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_stress_all_with_rand_reset.3705916273
98.88 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.19 0.07 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_tx_rx.1026153287
98.89 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.26 0.07 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_rx_parity_err.660316665
98.90 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.33 0.07 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_noise_filter.2005179746
98.91 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.40 0.07 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/270.uart_fifo_reset.2775412334
98.92 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.46 0.07 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/49.uart_fifo_reset.1801876873
98.94 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.53 0.07 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/73.uart_fifo_reset.2804567609
98.94 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.58 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_fifo_full.194285806
98.95 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.62 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/139.uart_fifo_reset.2579704725
98.96 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.67 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/140.uart_fifo_reset.2214341543
98.97 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.71 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_tx_rx.1672066565
98.97 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.76 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/19.uart_fifo_reset.3720467933
98.98 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.80 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/237.uart_fifo_reset.2837363954
98.99 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.85 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/251.uart_fifo_reset.1804657872
99.00 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.89 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/271.uart_fifo_reset.1345302051
99.00 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.94 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/273.uart_fifo_reset.561675791
99.01 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 98.98 0.05 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/55.uart_fifo_reset.435618411
99.01 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.01 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_fifo_full.967800568
99.02 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.03 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_fifo_reset.2713382033
99.02 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.05 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_long_xfer_wo_dly.2754773469
99.03 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.07 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/106.uart_fifo_reset.2632237185
99.03 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.10 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_fifo_full.1172095383
99.03 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.12 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/110.uart_fifo_reset.1289015679
99.04 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.14 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/112.uart_fifo_reset.2076063638
99.04 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.16 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/116.uart_fifo_reset.3591975164
99.04 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.19 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_tx_ovrd.24730775
99.05 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.21 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/136.uart_fifo_reset.2942245000
99.05 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.23 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_rx_parity_err.2228368171
99.06 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.25 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/142.uart_fifo_reset.1241464877
99.06 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.28 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/170.uart_fifo_reset.585459298
99.06 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.30 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/171.uart_fifo_reset.880269646
99.07 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.32 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/198.uart_fifo_reset.267794537
99.07 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.35 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/199.uart_fifo_reset.1108518738
99.07 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.37 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/202.uart_fifo_reset.3646519498
99.08 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.39 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/21.uart_fifo_reset.206227221
99.08 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.41 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/211.uart_fifo_reset.2850098131
99.09 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.44 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/213.uart_fifo_reset.4123871857
99.09 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.46 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/240.uart_fifo_reset.54147809
99.09 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.48 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/275.uart_fifo_reset.2775233049
99.10 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.50 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/278.uart_fifo_reset.2474785957
99.10 0.01 99.08 0.00 97.65 0.00 100.00 0.00 98.35 0.00 100.00 0.00 99.53 0.02 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/71.uart_fifo_reset.2658365425

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_aliasing.372127845
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_bit_bash.2055501646
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_hw_reset.3822729340
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3649887426
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_intr_test.1802581242
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_same_csr_outstanding.2497432213
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_errors.2364559962
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/0.uart_tl_intg_err.1647036437
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_bit_bash.1028800617
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_hw_reset.1528961314
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1387476192
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_csr_rw.1524897495
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_intr_test.3145659478
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_same_csr_outstanding.2231245621
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_errors.2197143344
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/1.uart_tl_intg_err.179615286
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.978038204
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_csr_rw.1349774522
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_intr_test.2923011515
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_same_csr_outstanding.2595801885
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_errors.535169987
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/10.uart_tl_intg_err.4235787990
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3348455984
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_csr_rw.1042892712
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_intr_test.62422108
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_same_csr_outstanding.2403427375
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_errors.3048256051
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/11.uart_tl_intg_err.1279110814
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1662113251
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_csr_rw.1572768400
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_intr_test.2740884973
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_same_csr_outstanding.3290516914
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_errors.993483230
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/12.uart_tl_intg_err.392214041
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.1905015112
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_csr_rw.84116177
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_intr_test.1002210819
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_same_csr_outstanding.2320239655
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/13.uart_tl_errors.3797280563
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.850824618
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_csr_rw.1487955911
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_intr_test.882285217
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_same_csr_outstanding.375010969
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_errors.3043107234
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/14.uart_tl_intg_err.618245665
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1900949787
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_csr_rw.3162159240
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_intr_test.3856856405
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_same_csr_outstanding.335091083
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/15.uart_tl_errors.358423158
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.1980072159
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_csr_rw.1399536240
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_intr_test.1844988851
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_same_csr_outstanding.1853094801
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_errors.2428240699
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/16.uart_tl_intg_err.1959160922
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3515186594
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_csr_rw.2443425211
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_intr_test.2499170689
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_same_csr_outstanding.720962059
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_errors.3174407738
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/17.uart_tl_intg_err.4051928661
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.576330865
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_csr_rw.1290336941
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_intr_test.3233708720
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_same_csr_outstanding.2195723718
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_errors.147230956
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/18.uart_tl_intg_err.1194909927
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3877693270
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_csr_rw.4115402327
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_intr_test.3825266948
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_same_csr_outstanding.2657411203
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_errors.3183195552
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/19.uart_tl_intg_err.2687319792
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_aliasing.148375495
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_bit_bash.739650959
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_hw_reset.3787294785
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.132169626
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_csr_rw.2982753860
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_intr_test.2500165271
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_same_csr_outstanding.907925591
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_errors.2011887397
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/2.uart_tl_intg_err.278296206
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/20.uart_intr_test.4268860208
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/21.uart_intr_test.1335078645
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/22.uart_intr_test.1176433840
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/23.uart_intr_test.164213488
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/24.uart_intr_test.3875763896
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/25.uart_intr_test.4176224404
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/26.uart_intr_test.3441324315
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/27.uart_intr_test.2827213401
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/28.uart_intr_test.293298267
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/29.uart_intr_test.2376706586
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_aliasing.2121456134
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_bit_bash.2281041107
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_hw_reset.3577435237
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3817058111
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_csr_rw.2960020476
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_intr_test.4288650629
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_same_csr_outstanding.2245058128
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/3.uart_tl_errors.3406195931
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/30.uart_intr_test.1513581735
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/31.uart_intr_test.912877299
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/32.uart_intr_test.2252942109
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/33.uart_intr_test.793714942
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/34.uart_intr_test.178419230
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/35.uart_intr_test.3413112079
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/36.uart_intr_test.246014118
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/37.uart_intr_test.3167060495
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/38.uart_intr_test.3538143239
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/39.uart_intr_test.4057174314
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_aliasing.1620836765
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_bit_bash.3519067098
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_hw_reset.711308095
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.111789418
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_csr_rw.163641548
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_intr_test.2657682192
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_same_csr_outstanding.3101684180
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_errors.3067192398
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/4.uart_tl_intg_err.3148741233
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/40.uart_intr_test.1063485828
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/41.uart_intr_test.3952661115
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/42.uart_intr_test.1549222635
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/43.uart_intr_test.3848663203
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/cover_reg_top/44.uart_intr_test.1852202483
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/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_rx_parity_err.1444811024
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/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.3410266252
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_tx_rx.3672845352
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/80.uart_fifo_reset.1995112545
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/80.uart_stress_all_with_rand_reset.1943891405
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/81.uart_fifo_reset.1656550202
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/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/82.uart_fifo_reset.507906765
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/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/83.uart_fifo_reset.1121534308
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/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/86.uart_fifo_reset.276567722
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/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/87.uart_fifo_reset.4056377249
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/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/88.uart_fifo_reset.98996848
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/88.uart_stress_all_with_rand_reset.1094142285
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/89.uart_fifo_reset.2848905587
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/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_alert_test.416341118
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_fifo_full.942460652
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.353827369
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/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/91.uart_fifo_reset.790168847
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/91.uart_stress_all_with_rand_reset.2500395431
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/92.uart_fifo_reset.488858747
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/92.uart_stress_all_with_rand_reset.2220074656
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/93.uart_fifo_reset.1685060597
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/93.uart_stress_all_with_rand_reset.2858125512
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/94.uart_fifo_reset.3235926310
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/94.uart_stress_all_with_rand_reset.509170005
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/95.uart_fifo_reset.619242046
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/95.uart_stress_all_with_rand_reset.1371390430
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/96.uart_fifo_reset.4173625889
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/96.uart_stress_all_with_rand_reset.3212904165
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/97.uart_fifo_reset.3701746266
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/97.uart_stress_all_with_rand_reset.2237754780
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/98.uart_fifo_reset.2118627986
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/98.uart_stress_all_with_rand_reset.1068061793
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/99.uart_fifo_reset.2004589370



Total test records in report: 1311
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_smoke.4175880677 Oct 09 05:26:08 AM UTC 24 Oct 09 05:26:11 AM UTC 24 128703199 ps
T2 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_rx_start_bit_filter.2468559536 Oct 09 05:26:12 AM UTC 24 Oct 09 05:26:15 AM UTC 24 3868193688 ps
T3 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_loopback.2366518009 Oct 09 05:26:14 AM UTC 24 Oct 09 05:26:19 AM UTC 24 3001888550 ps
T4 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_tx_rx.56248091 Oct 09 05:26:08 AM UTC 24 Oct 09 05:26:19 AM UTC 24 8930781968 ps
T5 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_tx_ovrd.2397512834 Oct 09 05:26:14 AM UTC 24 Oct 09 05:26:19 AM UTC 24 662608463 ps
T6 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_alert_test.921200671 Oct 09 05:26:17 AM UTC 24 Oct 09 05:26:19 AM UTC 24 36451662 ps
T7 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_sec_cm.2205244493 Oct 09 05:26:17 AM UTC 24 Oct 09 05:26:19 AM UTC 24 98848442 ps
T8 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_rx_oversample.2138744565 Oct 09 05:26:11 AM UTC 24 Oct 09 05:26:23 AM UTC 24 3007157712 ps
T9 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_smoke.1030982096 Oct 09 05:26:19 AM UTC 24 Oct 09 05:26:24 AM UTC 24 451993352 ps
T10 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_rx_oversample.4171357610 Oct 09 05:26:22 AM UTC 24 Oct 09 05:26:29 AM UTC 24 1271821742 ps
T11 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_fifo_reset.2114195492 Oct 09 05:26:11 AM UTC 24 Oct 09 05:26:30 AM UTC 24 24218803603 ps
T12 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_intr.156351167 Oct 09 05:26:12 AM UTC 24 Oct 09 05:26:32 AM UTC 24 35559220819 ps
T14 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_rx_start_bit_filter.2006215348 Oct 09 05:26:25 AM UTC 24 Oct 09 05:26:32 AM UTC 24 2615193202 ps
T29 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_alert_test.1888104734 Oct 09 05:26:33 AM UTC 24 Oct 09 05:26:35 AM UTC 24 24465973 ps
T30 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_sec_cm.661359655 Oct 09 05:26:33 AM UTC 24 Oct 09 05:26:35 AM UTC 24 62679116 ps
T43 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_intr.2955626495 Oct 09 05:26:24 AM UTC 24 Oct 09 05:26:36 AM UTC 24 57168231456 ps
T13 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_fifo_full.967800568 Oct 09 05:26:09 AM UTC 24 Oct 09 05:26:36 AM UTC 24 18430894554 ps
T15 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_smoke.1809654101 Oct 09 05:26:35 AM UTC 24 Oct 09 05:26:42 AM UTC 24 734542046 ps
T16 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_rx_parity_err.1735355411 Oct 09 05:26:12 AM UTC 24 Oct 09 05:26:42 AM UTC 24 50125068997 ps
T75 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_tx_rx.917284360 Oct 09 05:26:19 AM UTC 24 Oct 09 05:26:44 AM UTC 24 5917931269 ps
T76 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_rx_oversample.1543687527 Oct 09 05:26:39 AM UTC 24 Oct 09 05:26:44 AM UTC 24 1728461149 ps
T424 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_intr.2115138115 Oct 09 05:26:43 AM UTC 24 Oct 09 05:26:49 AM UTC 24 5099119101 ps
T18 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_stress_all_with_rand_reset.2727720527 Oct 09 05:26:15 AM UTC 24 Oct 09 05:26:49 AM UTC 24 9967300885 ps
T23 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_loopback.2598141735 Oct 09 05:26:50 AM UTC 24 Oct 09 05:26:53 AM UTC 24 1446619482 ps
T39 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_rx_start_bit_filter.3524703368 Oct 09 05:26:45 AM UTC 24 Oct 09 05:26:55 AM UTC 24 3156849694 ps
T40 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_loopback.2139075300 Oct 09 05:26:29 AM UTC 24 Oct 09 05:26:56 AM UTC 24 6221080313 ps
T32 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_sec_cm.2301334990 Oct 09 05:26:56 AM UTC 24 Oct 09 05:26:59 AM UTC 24 130161472 ps
T20 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_tx_ovrd.3336594126 Oct 09 05:26:27 AM UTC 24 Oct 09 05:27:00 AM UTC 24 6783150275 ps
T31 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_alert_test.1833514087 Oct 09 05:26:58 AM UTC 24 Oct 09 05:27:00 AM UTC 24 37066024 ps
T41 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_alert_test.1490826022 Oct 09 05:28:57 AM UTC 24 Oct 09 05:28:59 AM UTC 24 53147840 ps
T21 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_tx_ovrd.3574027404 Oct 09 05:26:50 AM UTC 24 Oct 09 05:27:04 AM UTC 24 8471280205 ps
T42 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_smoke.3484572269 Oct 09 05:27:01 AM UTC 24 Oct 09 05:27:05 AM UTC 24 406832840 ps
T130 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_noise_filter.3971102864 Oct 09 05:26:12 AM UTC 24 Oct 09 05:27:11 AM UTC 24 117840933982 ps
T131 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_tx_rx.3432709524 Oct 09 05:26:36 AM UTC 24 Oct 09 05:27:13 AM UTC 24 32730262816 ps
T17 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_intr.1598153262 Oct 09 05:27:07 AM UTC 24 Oct 09 05:27:13 AM UTC 24 7101181995 ps
T336 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_rx_start_bit_filter.1281368466 Oct 09 05:27:10 AM UTC 24 Oct 09 05:27:15 AM UTC 24 1982220787 ps
T454 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_loopback.74649293 Oct 09 05:27:12 AM UTC 24 Oct 09 05:27:17 AM UTC 24 543689406 ps
T455 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_alert_test.1930079298 Oct 09 05:27:17 AM UTC 24 Oct 09 05:27:19 AM UTC 24 13798098 ps
T87 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_sec_cm.490345884 Oct 09 05:27:17 AM UTC 24 Oct 09 05:27:19 AM UTC 24 128939553 ps
T44 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_smoke.1914128998 Oct 09 05:27:19 AM UTC 24 Oct 09 05:27:23 AM UTC 24 531366279 ps
T371 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_tx_ovrd.1569556056 Oct 09 05:27:12 AM UTC 24 Oct 09 05:27:24 AM UTC 24 7523812391 ps
T132 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_fifo_reset.4038686334 Oct 09 05:26:37 AM UTC 24 Oct 09 05:27:24 AM UTC 24 60757301818 ps
T134 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_tx_rx.2165742049 Oct 09 05:27:01 AM UTC 24 Oct 09 05:27:25 AM UTC 24 32895183950 ps
T27 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_stress_all_with_rand_reset.2620903782 Oct 09 05:27:15 AM UTC 24 Oct 09 05:27:31 AM UTC 24 4116839005 ps
T305 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_fifo_reset.4149669657 Oct 09 05:27:05 AM UTC 24 Oct 09 05:27:33 AM UTC 24 62509035512 ps
T364 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_rx_start_bit_filter.3884608421 Oct 09 05:27:30 AM UTC 24 Oct 09 05:27:34 AM UTC 24 2318788282 ps
T133 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_fifo_overflow.3205372370 Oct 09 05:26:37 AM UTC 24 Oct 09 05:27:35 AM UTC 24 141589038659 ps
T110 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_tx_rx.3994854170 Oct 09 05:27:21 AM UTC 24 Oct 09 05:27:39 AM UTC 24 36548114739 ps
T25 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_rx_parity_err.2674198572 Oct 09 05:26:45 AM UTC 24 Oct 09 05:27:39 AM UTC 24 19538261847 ps
T377 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_tx_ovrd.3088960618 Oct 09 05:27:34 AM UTC 24 Oct 09 05:27:40 AM UTC 24 553805638 ps
T88 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_sec_cm.3414711660 Oct 09 05:27:39 AM UTC 24 Oct 09 05:27:42 AM UTC 24 40283938 ps
T456 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_alert_test.2921384352 Oct 09 05:27:41 AM UTC 24 Oct 09 05:27:43 AM UTC 24 13753348 ps
T457 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_loopback.3209130201 Oct 09 05:27:34 AM UTC 24 Oct 09 05:27:45 AM UTC 24 4850624957 ps
T45 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_fifo_full.298415221 Oct 09 05:26:36 AM UTC 24 Oct 09 05:27:46 AM UTC 24 37497123783 ps
T404 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_smoke.2335827555 Oct 09 05:27:41 AM UTC 24 Oct 09 05:27:46 AM UTC 24 443388074 ps
T26 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_rx_oversample.568392199 Oct 09 05:27:07 AM UTC 24 Oct 09 05:27:49 AM UTC 24 4883917131 ps
T427 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_intr.63886004 Oct 09 05:27:46 AM UTC 24 Oct 09 05:27:51 AM UTC 24 3993793996 ps
T140 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_fifo_overflow.465225913 Oct 09 05:27:05 AM UTC 24 Oct 09 05:27:53 AM UTC 24 23724360886 ps
T435 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_rx_oversample.2087738391 Oct 09 05:27:26 AM UTC 24 Oct 09 05:27:54 AM UTC 24 4953294562 ps
T24 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_rx_oversample.1555006474 Oct 09 05:27:46 AM UTC 24 Oct 09 05:27:59 AM UTC 24 4215113823 ps
T111 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_rx_parity_err.3715420733 Oct 09 05:27:12 AM UTC 24 Oct 09 05:28:01 AM UTC 24 100131049682 ps
T108 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_intr.1507461075 Oct 09 05:27:26 AM UTC 24 Oct 09 05:28:03 AM UTC 24 79415565318 ps
T458 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_loopback.2382091671 Oct 09 05:27:52 AM UTC 24 Oct 09 05:28:04 AM UTC 24 6753227205 ps
T459 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_alert_test.3520390605 Oct 09 05:28:03 AM UTC 24 Oct 09 05:28:05 AM UTC 24 13711732 ps
T320 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_smoke.269829768 Oct 09 05:28:03 AM UTC 24 Oct 09 05:28:06 AM UTC 24 261766974 ps
T460 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_rx_oversample.2829870337 Oct 09 05:28:07 AM UTC 24 Oct 09 05:28:12 AM UTC 24 2011711008 ps
T138 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_rx_parity_err.294018896 Oct 09 05:27:32 AM UTC 24 Oct 09 05:28:17 AM UTC 24 91402419586 ps
T46 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_fifo_reset.837713353 Oct 09 05:27:46 AM UTC 24 Oct 09 05:28:20 AM UTC 24 48553614824 ps
T324 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_tx_ovrd.310240190 Oct 09 05:27:50 AM UTC 24 Oct 09 05:28:22 AM UTC 24 6844390957 ps
T137 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_fifo_full.448852382 Oct 09 05:28:05 AM UTC 24 Oct 09 05:28:24 AM UTC 24 23947605628 ps
T345 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_rx_start_bit_filter.986107302 Oct 09 05:27:49 AM UTC 24 Oct 09 05:28:25 AM UTC 24 25007522355 ps
T47 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_tx_ovrd.2283669654 Oct 09 05:28:46 AM UTC 24 Oct 09 05:29:00 AM UTC 24 6604851211 ps
T369 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_tx_ovrd.362745969 Oct 09 05:28:18 AM UTC 24 Oct 09 05:28:25 AM UTC 24 1152959872 ps
T135 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_fifo_overflow.2456811775 Oct 09 05:26:19 AM UTC 24 Oct 09 05:28:29 AM UTC 24 45143645265 ps
T139 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_fifo_reset.3673900556 Oct 09 05:28:07 AM UTC 24 Oct 09 05:28:31 AM UTC 24 18821882591 ps
T461 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_alert_test.4171758201 Oct 09 05:28:30 AM UTC 24 Oct 09 05:28:32 AM UTC 24 13107781 ps
T136 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_fifo_full.1844079740 Oct 09 05:27:21 AM UTC 24 Oct 09 05:28:33 AM UTC 24 40281696075 ps
T365 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_rx_start_bit_filter.3439661336 Oct 09 05:28:12 AM UTC 24 Oct 09 05:28:33 AM UTC 24 46576834744 ps
T338 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_smoke.4092279661 Oct 09 05:28:32 AM UTC 24 Oct 09 05:28:34 AM UTC 24 109046283 ps
T462 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_loopback.24559007 Oct 09 05:28:20 AM UTC 24 Oct 09 05:28:35 AM UTC 24 3155397847 ps
T146 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_fifo_overflow.3153369339 Oct 09 05:27:44 AM UTC 24 Oct 09 05:28:40 AM UTC 24 29613052933 ps
T28 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_stress_all_with_rand_reset.2120839309 Oct 09 05:27:39 AM UTC 24 Oct 09 05:28:45 AM UTC 24 16320777938 ps
T48 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_stress_all.4156859960 Oct 09 05:28:00 AM UTC 24 Oct 09 05:28:45 AM UTC 24 24021180178 ps
T311 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_fifo_reset.2109138859 Oct 09 05:27:24 AM UTC 24 Oct 09 05:28:47 AM UTC 24 46254798319 ps
T19 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_stress_all_with_rand_reset.1749330763 Oct 09 05:26:54 AM UTC 24 Oct 09 05:28:47 AM UTC 24 7399333740 ps
T325 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_smoke.3166079843 Oct 09 05:28:57 AM UTC 24 Oct 09 05:29:00 AM UTC 24 511990549 ps
T300 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_fifo_overflow.19370331 Oct 09 05:28:05 AM UTC 24 Oct 09 05:28:50 AM UTC 24 75314273584 ps
T340 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_rx_start_bit_filter.2734801894 Oct 09 05:28:42 AM UTC 24 Oct 09 05:28:52 AM UTC 24 3826792882 ps
T141 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_rx_parity_err.317170278 Oct 09 05:28:13 AM UTC 24 Oct 09 05:28:55 AM UTC 24 18382390334 ps
T109 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_tx_rx.118247469 Oct 09 05:28:33 AM UTC 24 Oct 09 05:28:55 AM UTC 24 34296847935 ps
T425 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_noise_filter.1161416055 Oct 09 05:28:40 AM UTC 24 Oct 09 05:28:56 AM UTC 24 30053590026 ps
T49 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_noise_filter.4200594910 Oct 09 05:27:49 AM UTC 24 Oct 09 05:29:00 AM UTC 24 25011765122 ps
T33 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_stress_all_with_rand_reset.3391907042 Oct 09 05:28:26 AM UTC 24 Oct 09 05:29:03 AM UTC 24 4311133075 ps
T463 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_rx_oversample.227661136 Oct 09 05:28:36 AM UTC 24 Oct 09 05:29:08 AM UTC 24 5857105128 ps
T436 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_loopback.2139609637 Oct 09 05:28:48 AM UTC 24 Oct 09 05:29:09 AM UTC 24 3957467418 ps
T34 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_stress_all_with_rand_reset.1184618116 Oct 09 05:28:00 AM UTC 24 Oct 09 05:29:13 AM UTC 24 4181768518 ps
T142 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_rx_parity_err.26866736 Oct 09 05:28:46 AM UTC 24 Oct 09 05:29:14 AM UTC 24 27641746903 ps
T209 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_fifo_reset.1467976521 Oct 09 05:26:21 AM UTC 24 Oct 09 05:29:16 AM UTC 24 70352770244 ps
T147 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_rx_parity_err.4003829244 Oct 09 05:27:50 AM UTC 24 Oct 09 05:29:18 AM UTC 24 33585914064 ps
T50 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_perf.3989417392 Oct 09 05:26:14 AM UTC 24 Oct 09 05:29:20 AM UTC 24 13782569665 ps
T464 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_loopback.3538623036 Oct 09 05:29:16 AM UTC 24 Oct 09 05:29:21 AM UTC 24 1789671535 ps
T349 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_tx_ovrd.3410266252 Oct 09 05:29:14 AM UTC 24 Oct 09 05:29:22 AM UTC 24 1093688626 ps
T465 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_alert_test.1459368748 Oct 09 05:29:22 AM UTC 24 Oct 09 05:29:24 AM UTC 24 28960124 ps
T309 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_noise_filter.3065107837 Oct 09 05:27:26 AM UTC 24 Oct 09 05:29:25 AM UTC 24 49278862427 ps
T303 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_intr.3706341690 Oct 09 05:28:09 AM UTC 24 Oct 09 05:29:26 AM UTC 24 24443362962 ps
T35 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_stress_all_with_rand_reset.3470722436 Oct 09 05:26:32 AM UTC 24 Oct 09 05:29:26 AM UTC 24 5045686791 ps
T144 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_fifo_full.727560882 Oct 09 05:28:34 AM UTC 24 Oct 09 05:29:26 AM UTC 24 78799650789 ps
T390 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_rx_start_bit_filter.3391914249 Oct 09 05:29:09 AM UTC 24 Oct 09 05:29:28 AM UTC 24 4840735041 ps
T293 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_tx_rx.3672845352 Oct 09 05:28:57 AM UTC 24 Oct 09 05:29:28 AM UTC 24 88512965632 ps
T397 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_smoke.4072775410 Oct 09 05:29:22 AM UTC 24 Oct 09 05:29:28 AM UTC 24 629027650 ps
T51 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_rx_oversample.153705421 Oct 09 05:29:01 AM UTC 24 Oct 09 05:29:29 AM UTC 24 5330282094 ps
T360 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_rx_start_bit_filter.597678917 Oct 09 05:29:29 AM UTC 24 Oct 09 05:29:33 AM UTC 24 3091856203 ps
T466 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_loopback.2573697313 Oct 09 05:29:33 AM UTC 24 Oct 09 05:29:36 AM UTC 24 562402122 ps
T430 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_noise_filter.99153500 Oct 09 05:29:09 AM UTC 24 Oct 09 05:29:36 AM UTC 24 9999628827 ps
T313 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_stress_all.780339343 Oct 09 05:28:55 AM UTC 24 Oct 09 05:29:36 AM UTC 24 66921106284 ps
T395 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_tx_ovrd.1247310347 Oct 09 05:29:30 AM UTC 24 Oct 09 05:29:45 AM UTC 24 7545242628 ps
T36 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_stress_all_with_rand_reset.2881997173 Oct 09 05:28:52 AM UTC 24 Oct 09 05:29:46 AM UTC 24 7819804614 ps
T52 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_fifo_overflow.2753193753 Oct 09 05:27:24 AM UTC 24 Oct 09 05:29:47 AM UTC 24 84057745174 ps
T467 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_alert_test.416341118 Oct 09 05:29:46 AM UTC 24 Oct 09 05:29:48 AM UTC 24 14184118 ps
T342 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_smoke.3068219846 Oct 09 05:29:46 AM UTC 24 Oct 09 05:29:50 AM UTC 24 629173597 ps
T288 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_fifo_full.4120855692 Oct 09 05:26:19 AM UTC 24 Oct 09 05:29:51 AM UTC 24 206590165745 ps
T22 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_intr.1310324174 Oct 09 05:28:37 AM UTC 24 Oct 09 05:29:55 AM UTC 24 26989309393 ps
T294 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_perf.2654460693 Oct 09 05:27:54 AM UTC 24 Oct 09 05:29:56 AM UTC 24 10510153707 ps
T143 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_fifo_overflow.3167279224 Oct 09 05:26:10 AM UTC 24 Oct 09 05:29:56 AM UTC 24 84965450858 ps
T164 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_rx_parity_err.3721771728 Oct 09 05:26:27 AM UTC 24 Oct 09 05:30:00 AM UTC 24 136882917884 ps
T370 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_intr.696823433 Oct 09 05:29:56 AM UTC 24 Oct 09 05:30:06 AM UTC 24 16078341888 ps
T37 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_stress_all_with_rand_reset.3415949263 Oct 09 05:29:37 AM UTC 24 Oct 09 05:30:10 AM UTC 24 27925462806 ps
T168 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_fifo_overflow.4276684499 Oct 09 05:29:01 AM UTC 24 Oct 09 05:30:10 AM UTC 24 63692164937 ps
T314 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/2.uart_noise_filter.2005179746 Oct 09 05:26:43 AM UTC 24 Oct 09 05:30:11 AM UTC 24 93512987034 ps
T162 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_fifo_overflow.353827369 Oct 09 05:29:27 AM UTC 24 Oct 09 05:30:13 AM UTC 24 26402327764 ps
T112 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_fifo_full.942460652 Oct 09 05:29:27 AM UTC 24 Oct 09 05:30:13 AM UTC 24 55028335661 ps
T468 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_alert_test.1470967084 Oct 09 05:30:14 AM UTC 24 Oct 09 05:30:16 AM UTC 24 47187341 ps
T145 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_fifo_overflow.1006420333 Oct 09 05:28:34 AM UTC 24 Oct 09 05:30:20 AM UTC 24 50484667263 ps
T292 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_tx_rx.1729027615 Oct 09 05:29:25 AM UTC 24 Oct 09 05:30:20 AM UTC 24 72543749764 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_smoke.1088079446 Oct 09 05:30:17 AM UTC 24 Oct 09 05:30:21 AM UTC 24 685867111 ps
T348 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_noise_filter.1167363906 Oct 09 05:29:29 AM UTC 24 Oct 09 05:30:22 AM UTC 24 48766174835 ps
T469 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_loopback.1278731485 Oct 09 05:30:10 AM UTC 24 Oct 09 05:30:23 AM UTC 24 7483852468 ps
T403 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_tx_ovrd.303547904 Oct 09 05:30:07 AM UTC 24 Oct 09 05:30:25 AM UTC 24 6494337468 ps
T290 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_noise_filter.2747498954 Oct 09 05:26:24 AM UTC 24 Oct 09 05:30:25 AM UTC 24 85226126752 ps
T426 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_intr.4172491890 Oct 09 05:29:28 AM UTC 24 Oct 09 05:30:25 AM UTC 24 14387963128 ps
T204 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_fifo_reset.1871749652 Oct 09 05:28:35 AM UTC 24 Oct 09 05:30:27 AM UTC 24 55907643662 ps
T372 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_rx_start_bit_filter.1474105248 Oct 09 05:30:26 AM UTC 24 Oct 09 05:30:29 AM UTC 24 6842781935 ps
T161 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_fifo_full.93277875 Oct 09 05:27:03 AM UTC 24 Oct 09 05:30:29 AM UTC 24 92714306346 ps
T291 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_fifo_full.194285806 Oct 09 05:29:48 AM UTC 24 Oct 09 05:30:31 AM UTC 24 23656214117 ps
T470 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_loopback.268165742 Oct 09 05:30:30 AM UTC 24 Oct 09 05:30:35 AM UTC 24 1779388682 ps
T312 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/7.uart_long_xfer_wo_dly.416870578 Oct 09 05:28:51 AM UTC 24 Oct 09 05:30:35 AM UTC 24 111151791496 ps
T471 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_rx_oversample.703870464 Oct 09 05:29:28 AM UTC 24 Oct 09 05:30:40 AM UTC 24 7453034778 ps
T289 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_noise_filter.830879552 Oct 09 05:29:57 AM UTC 24 Oct 09 05:30:42 AM UTC 24 106555851356 ps
T472 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_alert_test.102828827 Oct 09 05:30:43 AM UTC 24 Oct 09 05:30:45 AM UTC 24 31869714 ps
T473 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_rx_oversample.2691667117 Oct 09 05:29:51 AM UTC 24 Oct 09 05:30:47 AM UTC 24 6103604019 ps
T319 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_tx_rx.1678671012 Oct 09 05:29:47 AM UTC 24 Oct 09 05:30:47 AM UTC 24 72130809999 ps
T337 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_intr.1211261025 Oct 09 05:30:26 AM UTC 24 Oct 09 05:30:47 AM UTC 24 22967396990 ps
T315 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_tx_ovrd.2209389902 Oct 09 05:30:30 AM UTC 24 Oct 09 05:30:49 AM UTC 24 7737428005 ps
T331 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_smoke.2028756450 Oct 09 05:30:46 AM UTC 24 Oct 09 05:30:49 AM UTC 24 280939644 ps
T113 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_stress_all.2697536060 Oct 09 05:30:13 AM UTC 24 Oct 09 05:30:51 AM UTC 24 17897344584 ps
T38 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_stress_all_with_rand_reset.3737843325 Oct 09 05:30:36 AM UTC 24 Oct 09 05:30:53 AM UTC 24 1217965192 ps
T114 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_intr.2845228644 Oct 09 05:30:52 AM UTC 24 Oct 09 05:30:57 AM UTC 24 1831028597 ps
T376 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_fifo_overflow.1334091190 Oct 09 05:30:22 AM UTC 24 Oct 09 05:31:04 AM UTC 24 18493712856 ps
T332 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_fifo_full.3675073914 Oct 09 05:29:00 AM UTC 24 Oct 09 05:31:04 AM UTC 24 153841547652 ps
T366 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_rx_start_bit_filter.183706766 Oct 09 05:30:57 AM UTC 24 Oct 09 05:31:04 AM UTC 24 3750624956 ps
T307 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_perf.3868055779 Oct 09 05:27:13 AM UTC 24 Oct 09 05:31:10 AM UTC 24 27117800138 ps
T155 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_stress_all_with_rand_reset.3050706338 Oct 09 05:29:19 AM UTC 24 Oct 09 05:31:12 AM UTC 24 87402540019 ps
T238 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_fifo_reset.2713382033 Oct 09 05:29:50 AM UTC 24 Oct 09 05:31:18 AM UTC 24 116487704301 ps
T89 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_stress_all_with_rand_reset.3248654564 Oct 09 05:30:12 AM UTC 24 Oct 09 05:31:19 AM UTC 24 10645530530 ps
T99 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_loopback.3886788300 Oct 09 05:31:05 AM UTC 24 Oct 09 05:31:20 AM UTC 24 7485260807 ps
T100 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_fifo_overflow.2468417943 Oct 09 05:29:48 AM UTC 24 Oct 09 05:31:20 AM UTC 24 162119142211 ps
T101 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/3.uart_noise_filter.2136462748 Oct 09 05:27:07 AM UTC 24 Oct 09 05:31:21 AM UTC 24 118234616704 ps
T102 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_alert_test.4017522053 Oct 09 05:31:20 AM UTC 24 Oct 09 05:31:22 AM UTC 24 39433854 ps
T103 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_fifo_reset.1239725397 Oct 09 05:30:50 AM UTC 24 Oct 09 05:31:24 AM UTC 24 58454543240 ps
T104 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_rx_oversample.2629205626 Oct 09 05:30:50 AM UTC 24 Oct 09 05:31:26 AM UTC 24 5932886895 ps
T105 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_stress_all.3332495470 Oct 09 05:30:42 AM UTC 24 Oct 09 05:31:27 AM UTC 24 53055947363 ps
T106 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_tx_rx.47091315 Oct 09 05:30:48 AM UTC 24 Oct 09 05:31:27 AM UTC 24 54146137441 ps
T107 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/6.uart_tx_rx.504763709 Oct 09 05:28:03 AM UTC 24 Oct 09 05:31:28 AM UTC 24 92123817187 ps
T334 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_tx_ovrd.24730775 Oct 09 05:31:05 AM UTC 24 Oct 09 05:31:31 AM UTC 24 6334195336 ps
T148 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_rx_parity_err.2000599031 Oct 09 05:31:01 AM UTC 24 Oct 09 05:31:33 AM UTC 24 50699653750 ps
T474 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_rx_oversample.923789984 Oct 09 05:30:24 AM UTC 24 Oct 09 05:31:35 AM UTC 24 5399638304 ps
T428 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_noise_filter.4128030969 Oct 09 05:30:54 AM UTC 24 Oct 09 05:31:37 AM UTC 24 67980843171 ps
T387 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_smoke.777205442 Oct 09 05:31:20 AM UTC 24 Oct 09 05:31:38 AM UTC 24 6032428237 ps
T333 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_tx_ovrd.627639199 Oct 09 05:31:31 AM UTC 24 Oct 09 05:31:42 AM UTC 24 1302864640 ps
T375 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_rx_start_bit_filter.1394439813 Oct 09 05:29:58 AM UTC 24 Oct 09 05:31:42 AM UTC 24 49822552241 ps
T475 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_loopback.3656754410 Oct 09 05:31:34 AM UTC 24 Oct 09 05:31:44 AM UTC 24 9499610407 ps
T476 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_alert_test.1129154166 Oct 09 05:31:43 AM UTC 24 Oct 09 05:31:44 AM UTC 24 20828145 ps
T301 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_tx_rx.2095193182 Oct 09 05:27:42 AM UTC 24 Oct 09 05:31:46 AM UTC 24 78019348263 ps
T176 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_fifo_reset.2918536582 Oct 09 05:31:25 AM UTC 24 Oct 09 05:31:46 AM UTC 24 32027810722 ps
T328 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_smoke.1413102872 Oct 09 05:31:45 AM UTC 24 Oct 09 05:31:47 AM UTC 24 139326508 ps
T117 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_intr.3956666426 Oct 09 05:29:04 AM UTC 24 Oct 09 05:31:48 AM UTC 24 256371556999 ps
T157 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/10.uart_rx_parity_err.4294262015 Oct 09 05:30:01 AM UTC 24 Oct 09 05:31:49 AM UTC 24 122921394687 ps
T220 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_fifo_reset.1739390958 Oct 09 05:30:23 AM UTC 24 Oct 09 05:31:50 AM UTC 24 85316867598 ps
T341 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_noise_filter.3131790768 Oct 09 05:31:28 AM UTC 24 Oct 09 05:31:50 AM UTC 24 67451441735 ps
T368 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_rx_start_bit_filter.3863716469 Oct 09 05:31:51 AM UTC 24 Oct 09 05:31:58 AM UTC 24 4788077021 ps
T310 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_perf.4155065716 Oct 09 05:27:37 AM UTC 24 Oct 09 05:32:00 AM UTC 24 20954861309 ps
T367 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_rx_start_bit_filter.929575115 Oct 09 05:31:28 AM UTC 24 Oct 09 05:32:04 AM UTC 24 40304112028 ps
T327 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_fifo_full.116877814 Oct 09 05:31:47 AM UTC 24 Oct 09 05:32:05 AM UTC 24 23672917455 ps
T374 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_tx_ovrd.3297293714 Oct 09 05:32:02 AM UTC 24 Oct 09 05:32:05 AM UTC 24 1146487499 ps
T437 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_intr.3399800021 Oct 09 05:31:50 AM UTC 24 Oct 09 05:32:07 AM UTC 24 20346628323 ps
T434 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_stress_all_with_rand_reset.3891552785 Oct 09 05:31:39 AM UTC 24 Oct 09 05:32:07 AM UTC 24 3191097836 ps
T378 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_perf.3526109573 Oct 09 05:30:32 AM UTC 24 Oct 09 05:32:07 AM UTC 24 6005305768 ps
T429 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_fifo_reset.3040955711 Oct 09 05:31:48 AM UTC 24 Oct 09 05:32:08 AM UTC 24 5612909554 ps
T308 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_long_xfer_wo_dly.3739045453 Oct 09 05:29:17 AM UTC 24 Oct 09 05:32:08 AM UTC 24 93814057411 ps
T477 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_alert_test.1872065401 Oct 09 05:32:08 AM UTC 24 Oct 09 05:32:10 AM UTC 24 31791659 ps
T415 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_smoke.398141347 Oct 09 05:32:09 AM UTC 24 Oct 09 05:32:12 AM UTC 24 486107685 ps
T478 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_rx_oversample.3695566515 Oct 09 05:31:49 AM UTC 24 Oct 09 05:32:19 AM UTC 24 2760238498 ps
T479 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_loopback.3557174440 Oct 09 05:32:05 AM UTC 24 Oct 09 05:32:21 AM UTC 24 7375951225 ps
T384 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/1.uart_perf.4242443679 Oct 09 05:26:31 AM UTC 24 Oct 09 05:32:24 AM UTC 24 5818747790 ps
T299 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_rx_parity_err.3986342714 Oct 09 05:31:29 AM UTC 24 Oct 09 05:32:24 AM UTC 24 50621302071 ps
T480 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_rx_oversample.3237462405 Oct 09 05:32:22 AM UTC 24 Oct 09 05:32:24 AM UTC 24 1397983207 ps
T481 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_rx_oversample.1761205119 Oct 09 05:31:27 AM UTC 24 Oct 09 05:32:29 AM UTC 24 6402951904 ps
T321 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_fifo_full.1172095383 Oct 09 05:30:20 AM UTC 24 Oct 09 05:34:22 AM UTC 24 168383450859 ps
T205 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/8.uart_fifo_reset.2210735487 Oct 09 05:29:01 AM UTC 24 Oct 09 05:32:31 AM UTC 24 127732064264 ps
T385 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_intr.2248522935 Oct 09 05:31:28 AM UTC 24 Oct 09 05:32:32 AM UTC 24 66395478632 ps
T482 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_intr.3516634452 Oct 09 05:32:25 AM UTC 24 Oct 09 05:32:32 AM UTC 24 6708832995 ps
T177 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/5.uart_fifo_full.608586417 Oct 09 05:27:44 AM UTC 24 Oct 09 05:32:35 AM UTC 24 122262431070 ps
T318 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_tx_rx.2335141019 Oct 09 05:31:21 AM UTC 24 Oct 09 05:32:36 AM UTC 24 222779934181 ps
T483 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_loopback.1227370941 Oct 09 05:32:32 AM UTC 24 Oct 09 05:32:38 AM UTC 24 4808824639 ps
T484 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_alert_test.3212356676 Oct 09 05:32:38 AM UTC 24 Oct 09 05:32:40 AM UTC 24 11413550 ps
T380 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_fifo_full.2610055141 Oct 09 05:32:10 AM UTC 24 Oct 09 05:32:41 AM UTC 24 54725401567 ps
T383 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/11.uart_tx_rx.1089250796 Oct 09 05:30:20 AM UTC 24 Oct 09 05:32:43 AM UTC 24 37283055120 ps
T391 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_fifo_full.3980370380 Oct 09 05:31:21 AM UTC 24 Oct 09 05:32:43 AM UTC 24 39818550919 ps
T406 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_tx_ovrd.4131618884 Oct 09 05:32:31 AM UTC 24 Oct 09 05:32:43 AM UTC 24 8508562935 ps
T120 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/12.uart_stress_all_with_rand_reset.3705916273 Oct 09 05:31:13 AM UTC 24 Oct 09 05:32:44 AM UTC 24 15268031484 ps
T190 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_fifo_overflow.1682552877 Oct 09 05:32:13 AM UTC 24 Oct 09 05:32:47 AM UTC 24 59533252107 ps
T339 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_tx_rx.2529029749 Oct 09 05:32:09 AM UTC 24 Oct 09 05:32:49 AM UTC 24 71865729799 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_rx_parity_err.2228368171 Oct 09 05:31:58 AM UTC 24 Oct 09 05:32:50 AM UTC 24 25556071107 ps
T158 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/13.uart_fifo_overflow.2514223448 Oct 09 05:31:22 AM UTC 24 Oct 09 05:32:50 AM UTC 24 141009493481 ps
T485 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_rx_oversample.1216109572 Oct 09 05:32:45 AM UTC 24 Oct 09 05:32:55 AM UTC 24 3159024570 ps
T411 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_rx_start_bit_filter.255776826 Oct 09 05:32:51 AM UTC 24 Oct 09 05:32:57 AM UTC 24 5632346171 ps
T394 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_tx_ovrd.2095148338 Oct 09 05:32:55 AM UTC 24 Oct 09 05:32:59 AM UTC 24 1263670374 ps
T344 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_smoke.3927618571 Oct 09 05:32:42 AM UTC 24 Oct 09 05:32:59 AM UTC 24 5447345749 ps
T486 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_loopback.3464858581 Oct 09 05:32:58 AM UTC 24 Oct 09 05:33:03 AM UTC 24 1834258285 ps
T329 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_rx_start_bit_filter.564928824 Oct 09 05:32:26 AM UTC 24 Oct 09 05:33:08 AM UTC 24 83563023658 ps
T398 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_perf.2954490101 Oct 09 05:32:06 AM UTC 24 Oct 09 05:33:08 AM UTC 24 4016339775 ps
T326 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/0.uart_long_xfer_wo_dly.2026968292 Oct 09 05:26:15 AM UTC 24 Oct 09 05:33:10 AM UTC 24 73381407888 ps
T487 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_alert_test.3754422788 Oct 09 05:33:09 AM UTC 24 Oct 09 05:33:11 AM UTC 24 19749899 ps
T401 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_fifo_reset.218178377 Oct 09 05:32:44 AM UTC 24 Oct 09 05:33:14 AM UTC 24 59303282152 ps
T442 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_noise_filter.1719014590 Oct 09 05:32:50 AM UTC 24 Oct 09 05:33:14 AM UTC 24 12029309197 ps
T379 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_noise_filter.4037483552 Oct 09 05:31:50 AM UTC 24 Oct 09 05:33:17 AM UTC 24 158057314644 ps
T306 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_perf.3012078193 Oct 09 05:32:32 AM UTC 24 Oct 09 05:33:18 AM UTC 24 17873797352 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_fifo_full.2591321162 Oct 09 05:32:44 AM UTC 24 Oct 09 05:33:20 AM UTC 24 15959073286 ps
T90 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_stress_all_with_rand_reset.3573806619 Oct 09 05:32:36 AM UTC 24 Oct 09 05:33:25 AM UTC 24 10254862000 ps
T316 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/9.uart_long_xfer_wo_dly.2736560008 Oct 09 05:29:36 AM UTC 24 Oct 09 05:33:29 AM UTC 24 65955323268 ps
T115 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/4.uart_stress_all.3917022316 Oct 09 05:27:39 AM UTC 24 Oct 09 05:33:31 AM UTC 24 124310211153 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_fifo_overflow.87616560 Oct 09 05:31:47 AM UTC 24 Oct 09 05:33:31 AM UTC 24 107728818811 ps
T116 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/15.uart_rx_parity_err.660316665 Oct 09 05:32:30 AM UTC 24 Oct 09 05:33:32 AM UTC 24 64468523509 ps
T330 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/14.uart_tx_rx.1026153287 Oct 09 05:31:46 AM UTC 24 Oct 09 05:33:33 AM UTC 24 37208748657 ps
T416 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_tx_rx.1672066565 Oct 09 05:33:12 AM UTC 24 Oct 09 05:33:37 AM UTC 24 15123522529 ps
T488 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/16.uart_intr.1610230809 Oct 09 05:32:48 AM UTC 24 Oct 09 05:33:38 AM UTC 24 23506237025 ps
T402 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_rx_start_bit_filter.812053834 Oct 09 05:33:30 AM UTC 24 Oct 09 05:33:39 AM UTC 24 3193948233 ps
T489 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/17.uart_rx_oversample.2424087904 Oct 09 05:33:18 AM UTC 24 Oct 09 05:33:39 AM UTC 24 3244425141 ps
T490 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_loopback.1813401837 Oct 09 05:33:59 AM UTC 24 Oct 09 05:34:18 AM UTC 24 5417717220 ps
T296 /workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/coverage/default/18.uart_tx_rx.1014955561 Oct 09 05:33:42 AM UTC 24 Oct 09 05:34:21 AM UTC 24 35419977037 ps
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