| | | | | | | |
tb |
99.02 |
99.08 |
97.65 |
100.00 |
|
98.35 |
100.00 |
dut |
99.02 |
99.08 |
97.65 |
100.00 |
|
98.35 |
100.00 |
gen_alert_tx[0].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
tlul_assert_device |
100.00 |
|
|
|
|
|
100.00 |
u_reg |
99.06 |
98.77 |
98.68 |
100.00 |
|
97.85 |
100.00 |
u_alert_test |
100.00 |
100.00 |
|
|
|
|
|
u_chk |
100.00 |
100.00 |
|
100.00 |
|
|
100.00 |
u_chk |
100.00 |
|
|
100.00 |
|
|
|
u_tlul_data_integ_dec |
100.00 |
100.00 |
|
100.00 |
|
|
|
u_data_chk |
100.00 |
|
|
100.00 |
|
|
|
u_ctrl_llpbk |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_ctrl_nco |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_ctrl_nf |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_ctrl_parity_en |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_ctrl_parity_odd |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_ctrl_rx |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_ctrl_rxblvl |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_ctrl_slpbk |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_ctrl_tx |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_fifo_ctrl0_qe |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_fifo_ctrl_rxilvl |
96.30 |
100.00 |
88.89 |
|
|
100.00 |
|
wr_en_data_arb |
95.24 |
100.00 |
85.71 |
|
|
100.00 |
|
u_fifo_ctrl_rxrst |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_fifo_ctrl_txilvl |
96.30 |
100.00 |
88.89 |
|
|
100.00 |
|
wr_en_data_arb |
95.24 |
100.00 |
85.71 |
|
|
100.00 |
|
u_fifo_ctrl_txrst |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_fifo_status_rxlvl |
100.00 |
100.00 |
|
|
|
|
|
u_fifo_status_txlvl |
100.00 |
100.00 |
|
|
|
|
|
u_intr_enable_rx_break_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_rx_frame_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_rx_overflow |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_rx_parity_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_rx_timeout |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_rx_watermark |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_tx_done |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_tx_empty |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_enable_tx_watermark |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_intr_state_rx_break_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_intr_state_rx_frame_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_intr_state_rx_overflow |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_intr_state_rx_parity_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_intr_state_rx_timeout |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_intr_state_rx_watermark |
62.59 |
77.78 |
50.00 |
|
|
60.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_intr_state_tx_done |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_intr_state_tx_empty |
62.59 |
77.78 |
50.00 |
|
|
60.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_intr_state_tx_watermark |
62.59 |
77.78 |
50.00 |
|
|
60.00 |
|
wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
u_intr_test_rx_break_err |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_rx_frame_err |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_rx_overflow |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_rx_parity_err |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_rx_timeout |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_rx_watermark |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_tx_done |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_tx_empty |
100.00 |
100.00 |
|
|
|
|
|
u_intr_test_tx_watermark |
100.00 |
100.00 |
|
|
|
|
|
u_ovrd_txen |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_ovrd_txval |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_prim_reg_we_check |
100.00 |
100.00 |
|
100.00 |
|
|
|
u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_prim_onehot_check |
100.00 |
|
|
100.00 |
|
|
|
u_rdata |
100.00 |
100.00 |
|
|
|
|
|
u_reg_if |
98.67 |
97.14 |
97.53 |
|
|
100.00 |
100.00 |
u_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
u_rsp_intg_gen |
83.33 |
66.67 |
|
|
|
|
100.00 |
u_rsp_intg_gen |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_data_intg.u_tlul_data_integ_enc |
100.00 |
100.00 |
|
|
|
|
|
u_data_gen |
100.00 |
100.00 |
|
|
|
|
|
gen_rsp_intg.u_rsp_gen |
100.00 |
100.00 |
|
|
|
|
|
u_status_rxempty |
100.00 |
100.00 |
|
|
|
|
|
u_status_rxfull |
100.00 |
100.00 |
|
|
|
|
|
u_status_rxidle |
100.00 |
100.00 |
|
|
|
|
|
u_status_txempty |
100.00 |
100.00 |
|
|
|
|
|
u_status_txfull |
100.00 |
100.00 |
|
|
|
|
|
u_status_txidle |
100.00 |
100.00 |
|
|
|
|
|
u_timeout_ctrl_en |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_timeout_ctrl_val |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_val |
100.00 |
100.00 |
|
|
|
|
|
u_wdata |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_wdata0_qe |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
uart_core |
98.73 |
99.70 |
95.90 |
|
|
99.32 |
100.00 |
intr_hw_rx_break_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
intr_hw_rx_frame_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
intr_hw_rx_overflow |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
intr_hw_rx_parity_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
intr_hw_rx_timeout |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
intr_hw_rx_watermark |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
intr_hw_tx_done |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
intr_hw_tx_empty |
94.44 |
100.00 |
77.78 |
|
|
100.00 |
100.00 |
intr_hw_tx_watermark |
94.44 |
100.00 |
77.78 |
|
|
100.00 |
100.00 |
sync_rx |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_uart_rxfifo |
97.22 |
100.00 |
88.89 |
|
|
100.00 |
100.00 |
gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_uart_txfifo |
97.22 |
100.00 |
88.89 |
|
|
100.00 |
100.00 |
gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
uart_rx |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
uart_tx |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
uart_csr_assert |
100.00 |
|
|
|
|
|
100.00 |