Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2543

1

T1

1

T2

1

T3

1

auto[UartRx]

2543

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4429	1			T1	2		T2	2		T3	2
values[1]	54	1			T18	1		T28	2		T37	1
values[2]	43	1			T18	1		T28	2		T19	1
values[3]	54	1			T18	1		T27	2		T19	2
values[4]	61	1			T18	2		T27	1		T28	2
values[5]	53	1			T27	1		T19	2		T34	1
values[6]	62	1			T28	6		T19	1		T34	3
values[7]	57	1			T18	1		T27	2		T19	2
values[8]	75	1			T18	2		T27	1		T19	2
values[9]	71	1			T18	1		T28	1		T19	1
values[10]	78	1			T19	1		T34	2		T35	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2317	1			T1	1		T2	1		T3	1
auto[UartTx]	values[1]	19	1			T18	1		T28	1		T155	1
auto[UartTx]	values[2]	18	1			T18	1		T19	1		T124	1
auto[UartTx]	values[3]	18	1			T27	1		T35	1		T89	1
auto[UartTx]	values[4]	27	1			T18	1		T27	1		T28	1
auto[UartTx]	values[5]	15	1			T19	1		T34	1		T434	1
auto[UartTx]	values[6]	20	1			T28	3		T120	1		T90	1
auto[UartTx]	values[7]	17	1			T27	1		T19	1		T122	1
auto[UartTx]	values[8]	26	1			T27	1		T34	1		T155	1
auto[UartTx]	values[9]	27	1			T18	1		T19	1		T34	1
auto[UartTx]	values[10]	26	1			T120	1		T122	1		T91	1
auto[UartRx]	values[0]	2112	1			T1	1		T2	1		T3	1
auto[UartRx]	values[1]	35	1			T28	1		T37	1		T89	1
auto[UartRx]	values[2]	25	1			T28	2		T33	1		T35	1
auto[UartRx]	values[3]	36	1			T18	1		T27	1		T19	2
auto[UartRx]	values[4]	34	1			T18	1		T28	1		T34	1
auto[UartRx]	values[5]	38	1			T27	1		T19	1		T37	1
auto[UartRx]	values[6]	42	1			T28	3		T19	1		T34	3
auto[UartRx]	values[7]	40	1			T18	1		T27	1		T19	1
auto[UartRx]	values[8]	49	1			T18	2		T19	2		T33	1
auto[UartRx]	values[9]	44	1			T28	1		T35	1		T120	2
auto[UartRx]	values[10]	52	1			T19	1		T34	2		T35	1