Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	1784	1			T3	3		T8	7		T10	1
auto[BaudRate115200]	1503	1			T3	3		T4	1		T11	2
auto[BaudRate230400]	1553	1			T9	1		T11	1		T13	1
auto[BaudRate128Kbps]	1572	1			T2	1		T3	3		T4	1
auto[BaudRate256Kbps]	1665	1			T2	1		T9	1		T11	2
auto[BaudRate1Mbps]	1496	1			T1	2		T3	3		T4	1
auto[BaudRate1p5Mbps]	1043	1			T3	3		T4	2		T5	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	848	1			T16	9		T371	2		T132	5
freqs[25]	907	1			T12	2		T424	1		T130	19
freqs[48]	574	1			T131	6		T336	2		T435	12
freqs[50]	474	1			T1	2		T8	7		T13	6
freqs[100]	1003	1			T9	2		T75	4		T45	10

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	128	1			T371	1		T300	1		T289	1
auto[BaudRate9600]	freqs[25]	110	1			T130	1		T108	1		T138	2
auto[BaudRate9600]	freqs[48]	83	1			T435	12		T48	6		T311	2
auto[BaudRate9600]	freqs[50]	89	1			T8	7		T51	14		T387	1
auto[BaudRate9600]	freqs[100]	195	1			T75	1		T34	1		T143	2
auto[BaudRate115200]	freqs[24]	123	1			T305	2		T110	2		T137	2
auto[BaudRate115200]	freqs[25]	128	1			T12	1		T130	4		T138	1
auto[BaudRate115200]	freqs[48]	59	1			T48	7		T19	1		T358	1
auto[BaudRate115200]	freqs[50]	71	1			T13	2		T348	4		T434	1
auto[BaudRate115200]	freqs[100]	126	1			T75	1		T45	1		T303	1
auto[BaudRate230400]	freqs[24]	117	1			T16	2		T137	1		T50	2
auto[BaudRate230400]	freqs[25]	153	1			T424	1		T130	3		T108	1
auto[BaudRate230400]	freqs[48]	78	1			T131	2		T48	15		T19	3
auto[BaudRate230400]	freqs[50]	52	1			T13	1		T139	1		T33	1
auto[BaudRate230400]	freqs[100]	124	1			T9	1		T45	2		T34	3
auto[BaudRate128Kbps]	freqs[24]	127	1			T16	1		T132	1		T305	1
auto[BaudRate128Kbps]	freqs[25]	144	1			T12	1		T130	5		T142	2
auto[BaudRate128Kbps]	freqs[48]	70	1			T48	7		T311	1		T19	4
auto[BaudRate128Kbps]	freqs[50]	50	1			T139	1		T33	1		T348	1
auto[BaudRate128Kbps]	freqs[100]	143	1			T75	1		T45	3		T34	3
auto[BaudRate256Kbps]	freqs[24]	153	1			T16	5		T132	4		T305	2
auto[BaudRate256Kbps]	freqs[25]	143	1			T130	1		T138	3		T142	4
auto[BaudRate256Kbps]	freqs[48]	73	1			T131	1		T336	1		T320	1
auto[BaudRate256Kbps]	freqs[50]	71	1			T13	1		T33	2		T348	2
auto[BaudRate256Kbps]	freqs[100]	144	1			T9	1		T45	2		T34	4
auto[BaudRate1Mbps]	freqs[24]	140	1			T16	1		T371	1		T110	2
auto[BaudRate1Mbps]	freqs[25]	143	1			T130	3		T138	1		T436	6
auto[BaudRate1Mbps]	freqs[48]	104	1			T131	1		T338	1		T48	17
auto[BaudRate1Mbps]	freqs[50]	71	1			T1	2		T13	1		T139	1
auto[BaudRate1Mbps]	freqs[100]	129	1			T45	1		T34	3		T314	2
auto[BaudRate1p5Mbps]	freqs[25]	86	1			T130	2		T138	1		T144	2
auto[BaudRate1p5Mbps]	freqs[48]	107	1			T131	2		T336	1		T320	1
auto[BaudRate1p5Mbps]	freqs[50]	70	1			T13	1		T139	2		T331	1
auto[BaudRate1p5Mbps]	freqs[100]	142	1			T75	1		T45	1		T34	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded