Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.42	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	11	119	91.54

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	11	119	91.54	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	24661822	1			T3	2		T4	27		T8	1
all_levels[1]	144233	1			T16	1		T75	4		T18	7
all_levels[2]	2088	1			T75	1		T130	12		T131	2
all_levels[3]	937	1			T130	2		T131	2		T132	1
all_levels[4]	596	1			T16	1		T130	3		T131	1
all_levels[5]	463	1			T18	1		T130	3		T133	1
all_levels[6]	378	1			T13	1		T130	2		T134	1
all_levels[7]	304	1			T13	1		T110	1		T45	3
all_levels[8]	261	1			T131	1		T110	1		T46	1
all_levels[9]	231	1			T110	1		T45	2		T135	1
all_levels[10]	209	1			T16	1		T135	1		T136	4
all_levels[11]	157	1			T131	1		T135	1		T136	1
all_levels[12]	138	1			T13	1		T137	1		T135	2
all_levels[13]	134	1			T13	1		T132	2		T25	1
all_levels[14]	102	1			T45	1		T138	1		T46	1
all_levels[15]	97	1			T135	1		T139	4		T136	1
all_levels[16]	93	1			T140	1		T135	2		T141	1
all_levels[17]	85	1			T130	2		T137	1		T136	1
all_levels[18]	79	1			T45	1		T136	2		T142	1
all_levels[19]	59	1			T132	1		T25	1		T135	1
all_levels[20]	75	1			T18	1		T132	1		T135	2
all_levels[21]	56	1			T140	1		T136	3		T142	1
all_levels[22]	50	1			T13	1		T138	1		T141	1
all_levels[23]	44	1			T140	1		T137	1		T143	1
all_levels[24]	62	1			T137	1		T141	1		T144	1
all_levels[25]	38	1			T133	1		T25	1		T145	1
all_levels[26]	32	1			T16	1		T133	1		T143	1
all_levels[27]	40	1			T111	1		T136	1		T146	1
all_levels[28]	28	1			T13	1		T45	1		T136	1
all_levels[29]	26	1			T16	1		T46	1		T147	1
all_levels[30]	37	1			T140	1		T111	1		T145	1
all_levels[31]	20	1			T148	1		T149	1		T150	1
all_levels[32]	19	1			T142	1		T52	1		T151	1
all_levels[33]	24	1			T152	1		T153	1		T154	1
all_levels[34]	20	1			T52	1		T155	1		T156	1
all_levels[35]	18	1			T138	1		T157	1		T158	1
all_levels[36]	10	1			T142	1		T159	1		T160	1
all_levels[37]	17	1			T13	1		T161	1		T157	1
all_levels[38]	22	1			T45	1		T162	1		T163	1
all_levels[39]	15	1			T45	1		T136	1		T112	1
all_levels[40]	22	1			T164	2		T159	1		T160	1
all_levels[41]	14	1			T165	1		T166	1		T167	2
all_levels[42]	26	1			T168	1		T148	1		T169	1
all_levels[43]	6	1			T170	1		T171	1		T172	1
all_levels[44]	13	1			T45	1		T149	6		T173	1
all_levels[45]	12	1			T133	1		T174	1		T175	1
all_levels[46]	11	1			T46	1		T161	1		T176	1
all_levels[47]	15	1			T177	1		T178	1		T179	2
all_levels[48]	14	1			T138	1		T148	1		T177	1
all_levels[49]	18	1			T16	1		T164	1		T152	1
all_levels[50]	8	1			T144	1		T157	1		T180	2
all_levels[51]	8	1			T144	1		T153	1		T181	1
all_levels[52]	7	1			T182	1		T183	1		T184	1
all_levels[53]	9	1			T162	1		T185	1		T186	1
all_levels[54]	9	1			T164	2		T145	1		T187	1
all_levels[55]	9	1			T144	1		T112	1		T188	1
all_levels[56]	7	1			T168	1		T189	3		T184	1
all_levels[57]	7	1			T112	1		T190	1		T191	1
all_levels[58]	5	1			T100	1		T192	1		T193	1
all_levels[59]	7	1			T157	1		T194	1		T195	1
all_levels[60]	6	1			T161	1		T196	1		T179	1
all_levels[61]	6	1			T197	1		T198	1		T199	2
all_levels[62]	2	1			T200	1		T201	1		-	-
all_levels[63]	5	1			T202	1		T203	1		T201	3
all_levels[64]	73	1			T11	1		T140	1		T111	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24809640

1

T4

27

T11

12

T13

21

auto[1]

3798

1

T3

2

T8

1

T10

1

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	11	119	91.54	11

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[35]]	[auto[1]]	0	1	1
[all_levels[37]]	[auto[1]]	0	1	1
[all_levels[43]]	[auto[1]]	0	1	1
[all_levels[47]]	[auto[1]]	0	1	1
[all_levels[50]]	[auto[1]]	0	1	1
[all_levels[52]]	[auto[1]]	0	1	1
[all_levels[54]]	[auto[1]]	0	1	1
[all_levels[57] , all_levels[58]]	[auto[1]]	--	--	2
[all_levels[60]]	[auto[1]]	0	1	1
[all_levels[62]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	24658473	1			T4	27		T11	11		T13	14
all_levels[0]	auto[1]	3349	1			T3	2		T8	1		T10	1
all_levels[1]	auto[0]	144153	1			T16	1		T75	4		T18	7
all_levels[1]	auto[1]	80	1			T204	1		T89	1		T205	1
all_levels[2]	auto[0]	2064	1			T75	1		T130	12		T131	2
all_levels[2]	auto[1]	24	1			T206	5		T207	1		T208	1
all_levels[3]	auto[0]	911	1			T130	2		T131	2		T132	1
all_levels[3]	auto[1]	26	1			T46	1		T209	1		T210	1
all_levels[4]	auto[0]	567	1			T16	1		T130	3		T131	1
all_levels[4]	auto[1]	29	1			T176	1		T152	3		T167	2
all_levels[5]	auto[0]	449	1			T18	1		T130	3		T133	1
all_levels[5]	auto[1]	14	1			T169	2		T151	1		T211	1
all_levels[6]	auto[0]	350	1			T13	1		T130	2		T134	1
all_levels[6]	auto[1]	28	1			T212	1		T171	2		T213	6
all_levels[7]	auto[0]	283	1			T13	1		T110	1		T45	3
all_levels[7]	auto[1]	21	1			T214	1		T215	1		T216	4
all_levels[8]	auto[0]	251	1			T131	1		T110	1		T46	1
all_levels[8]	auto[1]	10	1			T150	1		T212	4		T217	2
all_levels[9]	auto[0]	209	1			T110	1		T45	2		T135	1
all_levels[9]	auto[1]	22	1			T218	1		T211	2		T219	2
all_levels[10]	auto[0]	192	1			T16	1		T135	1		T136	4
all_levels[10]	auto[1]	17	1			T220	2		T221	1		T222	1
all_levels[11]	auto[0]	151	1			T131	1		T135	1		T136	1
all_levels[11]	auto[1]	6	1			T209	1		T223	1		T224	1
all_levels[12]	auto[0]	129	1			T13	1		T137	1		T135	2
all_levels[12]	auto[1]	9	1			T225	1		T226	2		T227	1
all_levels[13]	auto[0]	123	1			T13	1		T132	1		T25	1
all_levels[13]	auto[1]	11	1			T132	1		T228	1		T229	1
all_levels[14]	auto[0]	98	1			T45	1		T138	1		T46	1
all_levels[14]	auto[1]	4	1			T230	1		T231	1		T232	2
all_levels[15]	auto[0]	84	1			T135	1		T139	1		T136	1
all_levels[15]	auto[1]	13	1			T139	3		T233	1		T234	1
all_levels[16]	auto[0]	88	1			T140	1		T135	2		T141	1
all_levels[16]	auto[1]	5	1			T235	1		T236	1		T237	1
all_levels[17]	auto[0]	77	1			T130	2		T137	1		T136	1
all_levels[17]	auto[1]	8	1			T238	1		T239	1		T240	1
all_levels[18]	auto[0]	70	1			T45	1		T136	2		T142	1
all_levels[18]	auto[1]	9	1			T241	1		T242	3		T243	1
all_levels[19]	auto[0]	58	1			T132	1		T25	1		T135	1
all_levels[19]	auto[1]	1	1			T244	1		-	-		-	-
all_levels[20]	auto[0]	65	1			T18	1		T132	1		T135	2
all_levels[20]	auto[1]	10	1			T245	3		T246	1		T247	6
all_levels[21]	auto[0]	54	1			T140	1		T136	3		T142	1
all_levels[21]	auto[1]	2	1			T248	1		T249	1		-	-
all_levels[22]	auto[0]	42	1			T13	1		T138	1		T141	1
all_levels[22]	auto[1]	8	1			T149	2		T250	2		T251	3
all_levels[23]	auto[0]	43	1			T140	1		T137	1		T143	1
all_levels[23]	auto[1]	1	1			T252	1		-	-		-	-
all_levels[24]	auto[0]	58	1			T137	1		T141	1		T144	1
all_levels[24]	auto[1]	4	1			T253	1		T214	1		T254	2
all_levels[25]	auto[0]	36	1			T133	1		T25	1		T145	1
all_levels[25]	auto[1]	2	1			T255	1		T256	1		-	-
all_levels[26]	auto[0]	28	1			T16	1		T133	1		T143	1
all_levels[26]	auto[1]	4	1			T257	1		T258	1		T259	1
all_levels[27]	auto[0]	32	1			T111	1		T136	1		T146	1
all_levels[27]	auto[1]	8	1			T260	5		T207	2		T261	1
all_levels[28]	auto[0]	24	1			T13	1		T45	1		T136	1
all_levels[28]	auto[1]	4	1			T262	3		T193	1		-	-
all_levels[29]	auto[0]	20	1			T16	1		T46	1		T147	1
all_levels[29]	auto[1]	6	1			T263	1		T264	1		T265	4
all_levels[30]	auto[0]	33	1			T140	1		T111	1		T145	1
all_levels[30]	auto[1]	4	1			T266	4		-	-		-	-
all_levels[31]	auto[0]	17	1			T148	1		T149	1		T150	1
all_levels[31]	auto[1]	3	1			T267	2		T203	1		-	-
all_levels[32]	auto[0]	15	1			T142	1		T52	1		T151	1
all_levels[32]	auto[1]	4	1			T268	1		T269	2		T270	1
all_levels[33]	auto[0]	23	1			T152	1		T153	1		T154	1
all_levels[33]	auto[1]	1	1			T271	1		-	-		-	-
all_levels[34]	auto[0]	18	1			T52	1		T155	1		T156	1
all_levels[34]	auto[1]	2	1			T272	2		-	-		-	-
all_levels[35]	auto[0]	18	1			T138	1		T157	1		T158	1
all_levels[36]	auto[0]	9	1			T142	1		T159	1		T160	1
all_levels[36]	auto[1]	1	1			T273	1		-	-		-	-
all_levels[37]	auto[0]	17	1			T13	1		T161	1		T157	1
all_levels[38]	auto[0]	19	1			T45	1		T162	1		T163	1
all_levels[38]	auto[1]	3	1			T274	1		T275	1		T276	1
all_levels[39]	auto[0]	14	1			T45	1		T136	1		T112	1
all_levels[39]	auto[1]	1	1			T210	1		-	-		-	-
all_levels[40]	auto[0]	18	1			T164	2		T159	1		T160	1
all_levels[40]	auto[1]	4	1			T277	4		-	-		-	-
all_levels[41]	auto[0]	13	1			T165	1		T166	1		T167	1
all_levels[41]	auto[1]	1	1			T167	1		-	-		-	-
all_levels[42]	auto[0]	21	1			T168	1		T148	1		T169	1
all_levels[42]	auto[1]	5	1			T278	1		T279	1		T263	1
all_levels[43]	auto[0]	6	1			T170	1		T171	1		T172	1
all_levels[44]	auto[0]	7	1			T45	1		T149	2		T173	1
all_levels[44]	auto[1]	6	1			T149	4		T280	1		T281	1
all_levels[45]	auto[0]	10	1			T133	1		T174	1		T175	1
all_levels[45]	auto[1]	2	1			T282	2		-	-		-	-
all_levels[46]	auto[0]	9	1			T46	1		T161	1		T176	1
all_levels[46]	auto[1]	2	1			T219	1		T200	1		-	-
all_levels[47]	auto[0]	15	1			T177	1		T178	1		T179	2
all_levels[48]	auto[0]	12	1			T138	1		T148	1		T177	1
all_levels[48]	auto[1]	2	1			T283	2		-	-		-	-
all_levels[49]	auto[0]	13	1			T16	1		T164	1		T152	1
all_levels[49]	auto[1]	5	1			T230	1		T284	4		-	-
all_levels[50]	auto[0]	8	1			T144	1		T157	1		T180	2
all_levels[51]	auto[0]	7	1			T144	1		T153	1		T181	1
all_levels[51]	auto[1]	1	1			T285	1		-	-		-	-
all_levels[52]	auto[0]	7	1			T182	1		T183	1		T184	1
all_levels[53]	auto[0]	8	1			T162	1		T185	1		T186	1
all_levels[53]	auto[1]	1	1			T286	1		-	-		-	-
all_levels[54]	auto[0]	9	1			T164	2		T145	1		T187	1
all_levels[55]	auto[0]	6	1			T144	1		T112	1		T188	1
all_levels[55]	auto[1]	3	1			T268	3		-	-		-	-
all_levels[56]	auto[0]	5	1			T168	1		T189	1		T184	1
all_levels[56]	auto[1]	2	1			T189	2		-	-		-	-
all_levels[57]	auto[0]	7	1			T112	1		T190	1		T191	1
all_levels[58]	auto[0]	5	1			T100	1		T192	1		T193	1
all_levels[59]	auto[0]	6	1			T157	1		T194	1		T195	1
all_levels[59]	auto[1]	1	1			T227	1		-	-		-	-
all_levels[60]	auto[0]	6	1			T161	1		T196	1		T179	1
all_levels[61]	auto[0]	5	1			T197	1		T198	1		T199	1
all_levels[61]	auto[1]	1	1			T199	1		-	-		-	-
all_levels[62]	auto[0]	2	1			T200	1		T201	1		-	-
all_levels[63]	auto[0]	3	1			T202	1		T203	1		T201	1
all_levels[63]	auto[1]	2	1			T201	2		-	-		-	-
all_levels[64]	auto[0]	67	1			T11	1		T140	1		T111	1
all_levels[64]	auto[1]	6	1			T268	1		T192	1		T287	1