Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	83465	1			T1	2		T2	2		T3	1
all_pins[1]	83465	1			T1	2		T2	2		T3	1
all_pins[2]	83465	1			T1	2		T2	2		T3	1
all_pins[3]	83465	1			T1	2		T2	2		T3	1
all_pins[4]	83465	1			T1	2		T2	2		T3	1
all_pins[5]	83465	1			T1	2		T2	2		T3	1
all_pins[6]	83465	1			T1	2		T2	2		T3	1
all_pins[7]	83465	1			T1	2		T2	2		T3	1
all_pins[8]	83465	1			T1	2		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	712183	1			T1	18		T2	18		T3	8
values[0x1]	39002	1			T3	1		T4	4		T8	2
transitions[0x0=>0x1]	29243	1			T4	3		T8	1		T10	1
transitions[0x1=>0x0]	29049	1			T3	1		T4	2		T8	1

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	63878	1			T1	2		T2	2		T3	1
all_pins[0]	values[0x1]	19587	1			T4	2		T8	1		T10	1
all_pins[0]	transitions[0x0=>0x1]	19059	1			T4	2		T8	1		T10	1
all_pins[0]	transitions[0x1=>0x0]	802	1			T110	3		T135	16		T136	1
all_pins[1]	values[0x0]	82135	1			T1	2		T2	2		T3	1
all_pins[1]	values[0x1]	1330	1			T12	25		T18	4		T17	8
all_pins[1]	transitions[0x0=>0x1]	1254	1			T12	25		T18	4		T17	8
all_pins[1]	transitions[0x1=>0x0]	1998	1			T16	1		T75	1		T130	8
all_pins[2]	values[0x0]	81391	1			T1	2		T2	2		T3	1
all_pins[2]	values[0x1]	2074	1			T16	1		T75	1		T130	8
all_pins[2]	transitions[0x0=>0x1]	2030	1			T16	1		T75	1		T130	8
all_pins[2]	transitions[0x1=>0x0]	207	1			T11	1		T12	2		T18	2
all_pins[3]	values[0x0]	83214	1			T1	2		T2	2		T3	1
all_pins[3]	values[0x1]	251	1			T11	1		T12	2		T18	2
all_pins[3]	transitions[0x0=>0x1]	209	1			T11	1		T12	2		T18	2
all_pins[3]	transitions[0x1=>0x0]	269	1			T12	16		T35	2		T36	2
all_pins[4]	values[0x0]	83154	1			T1	2		T2	2		T3	1
all_pins[4]	values[0x1]	311	1			T12	16		T35	3		T36	3
all_pins[4]	transitions[0x0=>0x1]	269	1			T12	16		T35	3		T36	3
all_pins[4]	transitions[0x1=>0x0]	116	1			T18	1		T19	1		T35	2
all_pins[5]	values[0x0]	83307	1			T1	2		T2	2		T3	1
all_pins[5]	values[0x1]	158	1			T18	1		T19	1		T35	2
all_pins[5]	transitions[0x0=>0x1]	126	1			T18	1		T19	1		T35	2
all_pins[5]	transitions[0x1=>0x0]	678	1			T12	4		T18	7		T130	2
all_pins[6]	values[0x0]	82755	1			T1	2		T2	2		T3	1
all_pins[6]	values[0x1]	710	1			T12	4		T18	7		T130	2
all_pins[6]	transitions[0x0=>0x1]	676	1			T12	4		T18	7		T130	2
all_pins[6]	transitions[0x1=>0x0]	267	1			T18	1		T25	1		T111	3
all_pins[7]	values[0x0]	83164	1			T1	2		T2	2		T3	1
all_pins[7]	values[0x1]	301	1			T18	1		T25	1		T111	3
all_pins[7]	transitions[0x0=>0x1]	162	1			T18	1		T25	1		T111	3
all_pins[7]	transitions[0x1=>0x0]	14141	1			T3	1		T4	2		T8	1
all_pins[8]	values[0x0]	69185	1			T1	2		T2	2		T4	1
all_pins[8]	values[0x1]	14280	1			T3	1		T4	2		T8	1
all_pins[8]	transitions[0x0=>0x1]	5458	1			T4	1		T11	2		T75	2
all_pins[8]	transitions[0x1=>0x0]	10571	1			T11	3		T13	2		T16	6