Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7055340	1			T4	2		T8	1		T10	1
all_levels[1]	1735481	1			T4	9		T16	7		T18	981
all_levels[2]	378349	1			T130	16		T131	2		T305	1
all_levels[3]	336430	1			T75	20		T130	5		T27	1
all_levels[4]	314194	1			T75	1		T18	1		T130	9
all_levels[5]	146370	1			T16	4		T18	1		T130	2
all_levels[6]	222920	1			T130	5		T27	1		T45	1
all_levels[7]	355619	1			T4	1		T18	1		T130	4
all_levels[8]	147100	1			T130	8		T45	22		T137	2
all_levels[9]	136169	1			T130	2		T133	1		T45	8
all_levels[10]	294884	1			T130	49		T27	2		T133	1
all_levels[11]	166410	1			T4	1		T130	2		T133	2
all_levels[12]	171670	1			T4	4		T130	45		T25	2
all_levels[13]	184008	1			T4	6		T130	3		T138	2
all_levels[14]	172809	1			T75	34		T18	1		T130	5
all_levels[15]	131756	1			T18	1		T130	6		T131	3
all_levels[16]	151568	1			T136	1		T19	6929		T34	3
all_levels[17]	134456	1			T18	1		T130	2		T133	9
all_levels[18]	233054	1			T18	1		T133	1		T135	3
all_levels[19]	390328	1			T16	3		T146	4		T28	1
all_levels[20]	184066	1			T131	3		T140	2		T146	3
all_levels[21]	173007	1			T135	1		T146	1		T19	1690
all_levels[22]	124396	1			T27	1		T146	3		T311	5
all_levels[23]	123680	1			T4	5		T130	32		T135	1
all_levels[24]	310823	1			T133	1		T135	1		T146	7
all_levels[25]	141645	1			T16	2		T131	7		T135	2
all_levels[26]	159766	1			T131	6		T27	1		T140	3
all_levels[27]	106132	1			T18	1		T25	1		T135	2
all_levels[28]	115202	1			T27	2		T146	1		T19	82
all_levels[29]	137245	1			T27	2		T139	4		T19	82
all_levels[30]	349791	1			T16	1		T135	1		T146	1
all_levels[31]	609145	1			T140	2		T28	105		T19	375
all_levels[32]	9419472	1			T11	12		T13	8		T16	5

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24809640

1

T4

27

T11

12

T13

21

auto[1]

3645

1

T4

1

T8

1

T10

1

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7053302	1			T4	2		T11	2		T13	13
all_levels[0]	auto[1]	2038	1			T8	1		T10	1		T11	6
all_levels[1]	auto[0]	1735234	1			T4	9		T16	7		T18	981
all_levels[1]	auto[1]	247	1			T132	2		T305	2		T46	1
all_levels[2]	auto[0]	378308	1			T130	16		T131	2		T305	1
all_levels[2]	auto[1]	41	1			T204	2		T220	2		T391	1
all_levels[3]	auto[0]	336344	1			T75	20		T130	5		T27	1
all_levels[3]	auto[1]	86	1			T135	1		T209	1		T422	4
all_levels[4]	auto[0]	314160	1			T75	1		T18	1		T130	9
all_levels[4]	auto[1]	34	1			T301	1		T379	1		T438	1
all_levels[5]	auto[0]	146324	1			T16	4		T18	1		T130	2
all_levels[5]	auto[1]	46	1			T209	1		T314	1		T169	1
all_levels[6]	auto[0]	222894	1			T130	5		T27	1		T45	1
all_levels[6]	auto[1]	26	1			T103	2		T339	1		T419	2
all_levels[7]	auto[0]	355531	1			T4	1		T18	1		T130	4
all_levels[7]	auto[1]	88	1			T303	7		T370	8		T385	22
all_levels[8]	auto[0]	147086	1			T130	8		T45	22		T137	2
all_levels[8]	auto[1]	14	1			T416	1		T409	1		T439	3
all_levels[9]	auto[0]	136132	1			T130	2		T133	1		T45	8
all_levels[9]	auto[1]	37	1			T140	1		T149	3		T218	2
all_levels[10]	auto[0]	294868	1			T130	49		T27	2		T133	1
all_levels[10]	auto[1]	16	1			T144	1		T440	1		T228	2
all_levels[11]	auto[0]	166393	1			T4	1		T130	2		T133	2
all_levels[11]	auto[1]	17	1			T302	1		T169	1		T441	1
all_levels[12]	auto[0]	171649	1			T4	4		T130	45		T25	2
all_levels[12]	auto[1]	21	1			T293	1		T442	1		T150	1
all_levels[13]	auto[0]	183986	1			T4	6		T130	3		T138	2
all_levels[13]	auto[1]	22	1			T295	1		T443	1		T183	1
all_levels[14]	auto[0]	172791	1			T75	34		T18	1		T130	5
all_levels[14]	auto[1]	18	1			T330	1		T189	1		T444	1
all_levels[15]	auto[0]	131658	1			T18	1		T130	5		T131	3
all_levels[15]	auto[1]	98	1			T130	1		T204	1		T319	1
all_levels[16]	auto[0]	151547	1			T136	1		T19	6929		T34	3
all_levels[16]	auto[1]	21	1			T189	2		T153	1		T166	2
all_levels[17]	auto[0]	134436	1			T18	1		T130	2		T133	8
all_levels[17]	auto[1]	20	1			T133	1		T430	1		T106	1
all_levels[18]	auto[0]	233041	1			T18	1		T133	1		T135	3
all_levels[18]	auto[1]	13	1			T445	1		T446	1		T447	1
all_levels[19]	auto[0]	390301	1			T16	2		T146	4		T28	1
all_levels[19]	auto[1]	27	1			T16	1		T311	1		T103	1
all_levels[20]	auto[0]	184052	1			T131	3		T140	2		T146	3
all_levels[20]	auto[1]	14	1			T311	1		T145	1		T448	1
all_levels[21]	auto[0]	172992	1			T135	1		T146	1		T19	1690
all_levels[21]	auto[1]	15	1			T150	2		T160	1		T255	1
all_levels[22]	auto[0]	124378	1			T27	1		T146	3		T311	4
all_levels[22]	auto[1]	18	1			T311	1		T206	5		T233	1
all_levels[23]	auto[0]	123658	1			T4	4		T130	32		T135	1
all_levels[23]	auto[1]	22	1			T4	1		T238	2		T115	1
all_levels[24]	auto[0]	310802	1			T133	1		T135	1		T146	7
all_levels[24]	auto[1]	21	1			T100	1		T449	1		T223	1
all_levels[25]	auto[0]	141632	1			T16	2		T131	7		T135	2
all_levels[25]	auto[1]	13	1			T450	1		T222	2		T451	1
all_levels[26]	auto[0]	159748	1			T131	5		T27	1		T140	3
all_levels[26]	auto[1]	18	1			T131	1		T452	1		T233	1
all_levels[27]	auto[0]	106107	1			T18	1		T25	1		T135	2
all_levels[27]	auto[1]	25	1			T425	1		T116	1		T453	1
all_levels[28]	auto[0]	115191	1			T27	2		T146	1		T19	82
all_levels[28]	auto[1]	11	1			T205	1		T189	1		T241	1
all_levels[29]	auto[0]	137225	1			T27	2		T139	2		T19	82
all_levels[29]	auto[1]	20	1			T139	2		T238	1		T343	1
all_levels[30]	auto[0]	349768	1			T16	1		T135	1		T146	1
all_levels[30]	auto[1]	23	1			T289	1		T245	2		T417	1
all_levels[31]	auto[0]	609132	1			T140	2		T28	105		T19	375
all_levels[31]	auto[1]	13	1			T221	2		T207	1		T215	1
all_levels[32]	auto[0]	9418970	1			T11	10		T13	8		T16	5
all_levels[32]	auto[1]	502	1			T11	2		T25	1		T111	1