Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	652	1			T18	7		T35	14		T36	14
all_values[1]	652	1			T18	7		T35	14		T36	14
all_values[2]	652	1			T18	7		T35	14		T36	14
all_values[3]	652	1			T18	7		T35	14		T36	14
all_values[4]	652	1			T18	7		T35	14		T36	14
all_values[5]	652	1			T18	7		T35	14		T36	14
all_values[6]	652	1			T18	7		T35	14		T36	14
all_values[7]	652	1			T18	7		T35	14		T36	14
all_values[8]	652	1			T18	7		T35	14		T36	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3174

1

T18

29

T35

82

T36

61

auto[1]

2694

1

T18

34

T35

44

T36

65

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1946

1

T18

20

T35

35

T36

46

auto[1]

3922

1

T18

43

T35

91

T36

80

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3509

1

T18

35

T35

67

T36

80

auto[1]

2359

1

T18

28

T35

59

T36

46

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	198	1			T35	8		T36	4		T38	5
all_values[0]	auto[0]	auto[1]	auto[1]	185	1			T18	3		T36	1		T38	3
all_values[0]	auto[1]	auto[0]	auto[1]	137	1			T18	2		T35	2		T36	5
all_values[0]	auto[1]	auto[1]	auto[1]	132	1			T18	2		T35	4		T36	4
all_values[1]	auto[0]	auto[0]	auto[0]	219	1			T18	1		T35	6		T36	4
all_values[1]	auto[0]	auto[1]	auto[0]	161	1			T18	3		T35	1		T36	6
all_values[1]	auto[1]	auto[0]	auto[1]	161	1			T18	2		T35	4		T36	2
all_values[1]	auto[1]	auto[1]	auto[1]	111	1			T18	1		T35	3		T36	2
all_values[2]	auto[0]	auto[0]	auto[0]	154	1			T18	1		T35	2		T36	5
all_values[2]	auto[0]	auto[0]	auto[1]	77	1			T35	3		T36	2		T120	3
all_values[2]	auto[0]	auto[1]	auto[0]	110	1			T18	4		T35	1		T36	3
all_values[2]	auto[0]	auto[1]	auto[1]	51	1			T35	2		T38	1		T121	1
all_values[2]	auto[1]	auto[0]	auto[1]	147	1			T18	1		T35	5		T36	3
all_values[2]	auto[1]	auto[1]	auto[1]	113	1			T18	1		T35	1		T36	1
all_values[3]	auto[0]	auto[0]	auto[0]	144	1			T35	6		T36	3		T38	1
all_values[3]	auto[0]	auto[0]	auto[1]	64	1			T35	1		T115	1		T121	1
all_values[3]	auto[0]	auto[1]	auto[0]	108	1			T18	2		T36	3		T38	4
all_values[3]	auto[0]	auto[1]	auto[1]	66	1			T18	1		T36	2		T38	2
all_values[3]	auto[1]	auto[0]	auto[1]	137	1			T18	3		T35	5		T36	2
all_values[3]	auto[1]	auto[1]	auto[1]	133	1			T18	1		T35	2		T36	4
all_values[4]	auto[0]	auto[0]	auto[0]	133	1			T18	2		T35	3		T36	4
all_values[4]	auto[0]	auto[0]	auto[1]	65	1			T18	1		T35	1		T120	2
all_values[4]	auto[0]	auto[1]	auto[0]	124	1			T18	1		T35	3		T36	2
all_values[4]	auto[0]	auto[1]	auto[1]	57	1			T35	1		T36	3		T120	1
all_values[4]	auto[1]	auto[0]	auto[1]	146	1			T18	1		T35	3		T36	4
all_values[4]	auto[1]	auto[1]	auto[1]	127	1			T18	2		T35	3		T36	1
all_values[5]	auto[0]	auto[0]	auto[0]	151	1			T18	2		T35	1		T36	2
all_values[5]	auto[0]	auto[0]	auto[1]	56	1			T35	2		T36	1		T38	2
all_values[5]	auto[0]	auto[1]	auto[0]	120	1			T18	2		T35	3		T36	2
all_values[5]	auto[0]	auto[1]	auto[1]	71	1			T36	4		T122	1		T123	2
all_values[5]	auto[1]	auto[0]	auto[1]	143	1			T18	1		T35	6		T36	2
all_values[5]	auto[1]	auto[1]	auto[1]	111	1			T18	2		T35	2		T36	3
all_values[6]	auto[0]	auto[0]	auto[0]	133	1			T18	1		T35	2		T36	4
all_values[6]	auto[0]	auto[0]	auto[1]	72	1			T35	1		T36	2		T124	1
all_values[6]	auto[0]	auto[1]	auto[0]	125	1			T35	4		T36	5		T38	3
all_values[6]	auto[0]	auto[1]	auto[1]	64	1			T18	2		T35	2		T36	1
all_values[6]	auto[1]	auto[0]	auto[1]	144	1			T18	2		T35	3		T36	2
all_values[6]	auto[1]	auto[1]	auto[1]	114	1			T18	2		T35	2		T38	4
all_values[7]	auto[0]	auto[0]	auto[0]	163	1			T18	1		T35	1		T36	2
all_values[7]	auto[0]	auto[0]	auto[1]	69	1			T18	1		T35	2		T36	2
all_values[7]	auto[0]	auto[1]	auto[0]	101	1			T35	2		T36	1		T38	2
all_values[7]	auto[0]	auto[1]	auto[1]	69	1			T18	1		T35	1		T36	4
all_values[7]	auto[1]	auto[0]	auto[1]	133	1			T18	2		T35	7		T36	1
all_values[7]	auto[1]	auto[1]	auto[1]	117	1			T18	2		T35	1		T36	4
all_values[8]	auto[0]	auto[0]	auto[1]	203	1			T18	4		T35	6		T36	3
all_values[8]	auto[0]	auto[1]	auto[1]	196	1			T18	2		T35	2		T36	5
all_values[8]	auto[1]	auto[0]	auto[1]	125	1			T18	1		T35	2		T36	2
all_values[8]	auto[1]	auto[1]	auto[1]	128	1			T35	4		T36	4		T38	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal