Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/uart-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_uart_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	61343982	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

15469568

1

T1

23

T2

225

T3

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	75588143	1			T1	3297		T2	206		T3	1675
values[0x0]	593975	1			T1	17		T2	195		T3	18
values[0x1]	631432	1			T1	17		T2	163		T3	34

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42653376	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

34160174

1

T1

1749

T2

266

T3

619

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	291390	1			T1	16		T2	1		T3	10
valid_sources[0x01]	354625	1			T1	9		T3	11		T10	7
valid_sources[0x02]	282268	1			T1	12		T3	6		T7	1
valid_sources[0x03]	276410	1			T1	12		T3	5		T4	4
valid_sources[0x04]	275971	1			T1	13		T3	11		T10	11
valid_sources[0x05]	268607	1			T1	15		T2	8		T3	5
valid_sources[0x06]	358143	1			T1	16		T2	2		T3	11
valid_sources[0x07]	315879	1			T1	16		T2	8		T3	10
valid_sources[0x08]	300937	1			T1	13		T3	4		T7	3
valid_sources[0x09]	287374	1			T1	13		T2	9		T3	3
valid_sources[0x0a]	290394	1			T1	13		T3	9		T10	10
valid_sources[0x0b]	282030	1			T1	9		T3	6		T10	14
valid_sources[0x0c]	273135	1			T1	15		T3	5		T10	5
valid_sources[0x0d]	316563	1			T1	15		T3	5		T10	8
valid_sources[0x0e]	315383	1			T1	14		T3	4		T7	1
valid_sources[0x0f]	258281	1			T1	10		T3	11		T7	1
valid_sources[0x10]	353282	1			T1	14		T3	1		T6	1
valid_sources[0x11]	277716	1			T1	11		T3	7		T10	15
valid_sources[0x12]	293558	1			T1	9		T3	3		T10	16
valid_sources[0x13]	417173	1			T1	4		T3	5		T7	2
valid_sources[0x14]	320651	1			T1	16		T3	6		T10	14
valid_sources[0x15]	272910	1			T1	9		T2	17		T3	2
valid_sources[0x16]	367075	1			T1	10		T3	9		T7	2
valid_sources[0x17]	339935	1			T1	10		T3	2		T10	7
valid_sources[0x18]	290647	1			T1	13		T2	1		T7	3
valid_sources[0x19]	322177	1			T1	20		T2	20		T3	22
valid_sources[0x1a]	302401	1			T1	21		T3	7		T10	6
valid_sources[0x1b]	309011	1			T1	16		T3	10		T7	1
valid_sources[0x1c]	272988	1			T1	15		T2	6		T3	7
valid_sources[0x1d]	303027	1			T1	17		T3	2		T7	7
valid_sources[0x1e]	287086	1			T1	15		T3	6		T10	10
valid_sources[0x1f]	308036	1			T1	9		T3	4		T7	1
valid_sources[0x20]	271963	1			T1	14		T3	4		T8	12
valid_sources[0x21]	289925	1			T1	9		T3	5		T7	9
valid_sources[0x22]	257371	1			T1	15		T3	6		T10	12
valid_sources[0x23]	311016	1			T1	15		T3	8		T10	7
valid_sources[0x24]	303990	1			T1	10		T3	8		T10	10
valid_sources[0x25]	264814	1			T1	12		T2	7		T3	3
valid_sources[0x26]	279523	1			T1	21		T2	7		T3	6
valid_sources[0x27]	299235	1			T1	20		T3	6		T10	12
valid_sources[0x28]	298162	1			T1	11		T3	7		T10	5
valid_sources[0x29]	416552	1			T1	8		T3	7		T10	9
valid_sources[0x2a]	288773	1			T1	11		T3	8		T7	1
valid_sources[0x2b]	326034	1			T1	11		T3	8		T7	4
valid_sources[0x2c]	347437	1			T1	8		T3	6		T10	10
valid_sources[0x2d]	288348	1			T1	15		T3	1		T10	10
valid_sources[0x2e]	286502	1			T1	12		T3	4		T10	12
valid_sources[0x2f]	315884	1			T1	18		T3	7		T7	6
valid_sources[0x30]	359817	1			T1	9		T3	5		T7	4
valid_sources[0x31]	262325	1			T1	19		T2	12		T3	7
valid_sources[0x32]	296583	1			T1	16		T3	8		T10	11
valid_sources[0x33]	283574	1			T1	13		T3	8		T10	7
valid_sources[0x34]	290728	1			T1	12		T2	10		T3	7
valid_sources[0x35]	277887	1			T1	12		T3	9		T10	13
valid_sources[0x36]	289671	1			T1	10		T3	6		T6	1
valid_sources[0x37]	289997	1			T1	16		T3	8		T7	2
valid_sources[0x38]	281792	1			T1	10		T3	7		T7	2
valid_sources[0x39]	275008	1			T1	14		T2	3		T3	3
valid_sources[0x3a]	291732	1			T1	15		T2	3		T3	4
valid_sources[0x3b]	324771	1			T1	11		T3	15		T7	4
valid_sources[0x3c]	260579	1			T1	16		T3	4		T10	15
valid_sources[0x3d]	289394	1			T1	14		T3	3		T9	1
valid_sources[0x3e]	262807	1			T1	10		T2	1		T3	8
valid_sources[0x3f]	284921	1			T1	14		T3	8		T10	10
valid_sources[0x40]	347854	1			T1	8		T3	6		T10	14
valid_sources[0x41]	272404	1			T1	5		T3	8		T10	10
valid_sources[0x42]	305190	1			T1	18		T2	22		T3	6
valid_sources[0x43]	287451	1			T1	12		T3	9		T10	10
valid_sources[0x44]	289715	1			T1	14		T3	6		T7	1
valid_sources[0x45]	308510	1			T1	17		T2	1		T3	7
valid_sources[0x46]	404886	1			T1	13		T2	10		T3	9
valid_sources[0x47]	296284	1			T1	14		T2	13		T3	11
valid_sources[0x48]	294822	1			T1	10		T3	7		T7	1
valid_sources[0x49]	269319	1			T1	13		T2	1		T3	6
valid_sources[0x4a]	285622	1			T1	10		T3	7		T10	11
valid_sources[0x4b]	348463	1			T1	14		T3	4		T10	6
valid_sources[0x4c]	408897	1			T1	12		T3	5		T7	2
valid_sources[0x4d]	423823	1			T1	14		T3	4		T10	13
valid_sources[0x4e]	280498	1			T1	13		T3	3		T7	1
valid_sources[0x4f]	360867	1			T1	13		T3	6		T10	6
valid_sources[0x50]	295315	1			T1	12		T2	1		T3	5
valid_sources[0x51]	285097	1			T1	17		T3	5		T7	1
valid_sources[0x52]	369531	1			T1	16		T2	1		T3	7
valid_sources[0x53]	323387	1			T1	5		T2	2		T3	2
valid_sources[0x54]	288781	1			T1	18		T3	7		T10	10
valid_sources[0x55]	306629	1			T1	15		T3	12		T7	2
valid_sources[0x56]	281002	1			T1	14		T3	5		T7	2
valid_sources[0x57]	283515	1			T1	19		T3	5		T10	9
valid_sources[0x58]	259407	1			T1	14		T3	3		T10	10
valid_sources[0x59]	367794	1			T1	13		T3	4		T7	4
valid_sources[0x5a]	293731	1			T1	17		T3	4		T10	3
valid_sources[0x5b]	270604	1			T1	14		T2	10		T3	9
valid_sources[0x5c]	278191	1			T1	11		T3	3		T10	9
valid_sources[0x5d]	275350	1			T1	13		T2	10		T3	4
valid_sources[0x5e]	339742	1			T1	15		T3	8		T7	1
valid_sources[0x5f]	262713	1			T1	9		T2	6		T3	5
valid_sources[0x60]	264006	1			T1	12		T3	7		T7	1
valid_sources[0x61]	273613	1			T1	7		T3	2		T10	8
valid_sources[0x62]	274861	1			T1	10		T3	10		T10	15
valid_sources[0x63]	282388	1			T1	7		T3	7		T10	8
valid_sources[0x64]	282968	1			T1	9		T3	2		T7	1
valid_sources[0x65]	260052	1			T1	7		T3	14		T10	10
valid_sources[0x66]	307180	1			T1	9		T3	12		T10	5
valid_sources[0x67]	273330	1			T1	9		T3	5		T10	7
valid_sources[0x68]	280287	1			T1	9		T2	5		T3	3
valid_sources[0x69]	281451	1			T1	20		T2	9		T3	3
valid_sources[0x6a]	323721	1			T1	13		T3	6		T10	13
valid_sources[0x6b]	284965	1			T1	10		T2	5		T3	10
valid_sources[0x6c]	303419	1			T1	12		T3	5		T10	9
valid_sources[0x6d]	271937	1			T1	13		T2	4		T3	9
valid_sources[0x6e]	273239	1			T1	13		T3	6		T10	14
valid_sources[0x6f]	259885	1			T1	11		T3	5		T10	14
valid_sources[0x70]	267427	1			T1	10		T3	6		T7	2
valid_sources[0x71]	270274	1			T1	18		T3	4		T7	2
valid_sources[0x72]	461517	1			T1	10		T3	8		T10	13
valid_sources[0x73]	291675	1			T1	10		T3	5		T10	3
valid_sources[0x74]	301577	1			T1	13		T2	7		T3	7
valid_sources[0x75]	269003	1			T1	5		T3	6		T10	9
valid_sources[0x76]	306521	1			T1	10		T2	17		T3	6
valid_sources[0x77]	276949	1			T1	12		T3	10		T7	2
valid_sources[0x78]	315339	1			T1	20		T3	3		T7	5
valid_sources[0x79]	268116	1			T1	15		T3	5		T10	14
valid_sources[0x7a]	287483	1			T1	9		T2	2		T3	8
valid_sources[0x7b]	283885	1			T1	9		T3	10		T10	9
valid_sources[0x7c]	281306	1			T1	23		T3	5		T7	3
valid_sources[0x7d]	299159	1			T1	21		T3	17		T10	8
valid_sources[0x7e]	313849	1			T1	15		T2	7		T3	10
valid_sources[0x7f]	265905	1			T1	14		T2	3		T3	6
valid_sources[0x80]	308643	1			T1	11		T2	11		T3	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14686805

1

T2

102

T3

6

T6

1

values[0x0]

all_enables

biggest_size

416129

1

T1

11

T2

86

T3

9

values[0x1]

all_enables

biggest_size

366634

1

T1

12

T2

37

T3

11